公开(公告)号：US11764119B2

公开(公告)日：2023-09-19

申请号：US17672939

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungheon Lee ,  Jaekang Koh ,  Hyukwoo Kwon ,  Munjun Kim ,  Taejong Han

IPC: H01L23/29 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L23/291 ,  H01L21/0228 ,  H01L23/3185

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

公开(公告)号：US11264294B2

公开(公告)日：2022-03-01

申请号：US16919307

申请日：2020-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungheon Lee ,  Jaekang Koh ,  Hyukwoo Kwon ,  Munjun Kim ,  Taejong Han

IPC: H01L21/02 ,  H01L23/29 ,  H01L23/31

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.