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公开(公告)号:US20240363469A1
公开(公告)日:2024-10-31
申请号:US18765696
申请日:2024-07-08
IPC分类号: H01L23/31 , H01L21/56 , H01L21/768 , H01L23/48 , H01L23/528 , H01L25/065
CPC分类号: H01L23/3185 , H01L21/56 , H01L21/76829 , H01L23/481 , H01L23/5283 , H01L25/0657
摘要: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.
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公开(公告)号:US12125822B2
公开(公告)日:2024-10-22
申请号:US17097059
申请日:2020-11-13
发明人: Che-Chia Yang , Shu-Shen Yeh , Po-Chen Lai , Ming-Chih Yew , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L25/065 , H01L23/00 , H01L23/31 , H01L25/00
CPC分类号: H01L25/0655 , H01L23/3185 , H01L23/562 , H01L24/16 , H01L25/50 , H01L2224/16157
摘要: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.
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公开(公告)号:US12119229B2
公开(公告)日:2024-10-15
申请号:US17727606
申请日:2022-04-22
发明人: Yu-Hsiang Hu , Wei-Yu Chen , Hung-Jui Kuo , Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号: H01L21/304 , H01L23/00 , H01L23/14 , H01L23/15 , H01L23/31 , H01L25/065 , H01L25/07 , H01L21/56
CPC分类号: H01L21/304 , H01L23/147 , H01L23/15 , H01L23/3121 , H01L23/3157 , H01L23/3185 , H01L23/3192 , H01L24/19 , H01L24/20 , H01L25/0655 , H01L25/072 , H01L21/561 , H01L2224/04105 , H01L2224/11 , H01L2224/12105 , H01L2224/16227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244
摘要: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.
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公开(公告)号:US12094791B2
公开(公告)日:2024-09-17
申请号:US17286737
申请日:2019-10-10
申请人: Hitachi Energy Ltd
IPC分类号: H01L23/10 , H01L21/56 , H01L23/051 , H01L23/31
CPC分类号: H01L23/051 , H01L21/565 , H01L23/10 , H01L23/3185
摘要: A power semiconductor device includes a semiconductor wafer having a junction and a junction termination laterally surrounding the junction. A protection layer covers the lateral side of the semiconductor wafer and covers the second main side at least in an area of the junction termination. A first metal disk is arranged on the first main side to cover the first main side of the semiconductor wafer. An interface between the first metal disk and the semiconductor wafer is a free floating interface. A metal layer sandwiched between the first metal disk and the semiconductor wafer.
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公开(公告)号:US12087654B2
公开(公告)日:2024-09-10
申请号:US18358914
申请日:2023-07-25
发明人: Yung-Chi Chu , Hung-Jui Kuo , Yu-Hsiang Hu , Sih-Hao Liao , Tian Hu
IPC分类号: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/48 , H01L23/58 , H01L27/146 , H01L31/0203
CPC分类号: H01L23/3192 , H01L21/56 , H01L23/3107 , H01L23/3185 , H01L23/481 , H01L23/585 , H01L24/24 , H01L24/82 , H01L27/14636 , H01L31/0203 , H01L2224/24105 , H01L2224/24155 , H01L2224/73267 , H01L2224/82101 , H01L2224/82106 , H01L2924/181
摘要: A semiconductor device includes an encapsulant including a first hollow region, a sensing die in the first hollow region of the encapsulant, and a redistribution structure disposed on the encapsulant and the sensing die and electrically coupled to the sensing die. A top width of the hollow region is greater than a bottom width of the hollow region. The redistribution structure includes a second hollow region which exposes a sensing area of the sensing die, and the redistribution structure is slanted downward from an edge of the device toward the sensing area.
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公开(公告)号:US20240282658A1
公开(公告)日:2024-08-22
申请号:US18169998
申请日:2023-02-16
IPC分类号: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/29 , H01L23/367
CPC分类号: H01L23/3185 , H01L21/561 , H01L23/29 , H01L23/291 , H01L23/3192 , H01L23/3675 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/95 , H01L2224/16225 , H01L2224/2732 , H01L2224/2741 , H01L2224/2745 , H01L2224/27462 , H01L2224/2783 , H01L2224/29083 , H01L2224/29111 , H01L2224/29139 , H01L2224/29147 , H01L2224/29181 , H01L2224/29186 , H01L2224/2919 , H01L2224/32153 , H01L2224/32221 , H01L2224/33183 , H01L2224/95 , H01L2924/0132 , H01L2924/0133 , H01L2924/04953 , H01L2924/07025
摘要: A semiconductor integrated circuit device includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting solder at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
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公开(公告)号:US20240274566A1
公开(公告)日:2024-08-15
申请号:US18432081
申请日:2024-02-05
IPC分类号: H01L23/00
CPC分类号: H01L24/20 , H01L23/3121 , H01L23/3135 , H01L23/3185 , H01L24/19 , H01L23/293 , H01L2224/19 , H01L2224/2101 , H01L2224/2105 , H01L2224/211 , H01L2224/214
摘要: A package structure includes a chip and a dielectric. The chip includes a chip connector disposed on an active surface of the chip. The dielectric is at least disposed on the active surface of the chip. The chip connector has a top surface and a side surface connected to the top surface. The dielectric does not directly cover part of the side surface close to the top surface.
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公开(公告)号:US20240274485A1
公开(公告)日:2024-08-15
申请号:US18324036
申请日:2023-05-25
发明人: Che Chi Shih , Ku-Feng Yang , Han-Yu Lin , Wei-Yen Woon , Szuya Liao
IPC分类号: H01L23/31 , H01L21/56 , H01L21/683 , H01L23/00
CPC分类号: H01L23/3157 , H01L21/56 , H01L21/6835 , H01L23/3185 , H01L24/29 , H01L24/32 , H01L24/83 , H01L23/291 , H01L23/298 , H01L23/5286 , H01L27/12 , H01L2221/68359 , H01L2221/68377 , H01L2224/29186 , H01L2224/32225 , H01L2224/83193 , H01L2224/83896 , H01L2924/0504 , H01L2924/05442 , H01L2924/059
摘要: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a power rail. The device further includes a carrier substrate bonded to the first interconnect structure and a first heat dissipation layer contacting the carrier substrate.
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公开(公告)号:US12057408B2
公开(公告)日:2024-08-06
申请号:US17171475
申请日:2021-02-09
发明人: Chulwoo Kim , Yanggyoo Jung , Soohyun Nam
IPC分类号: H01L23/00 , H01L23/16 , H01L23/31 , H01L23/367 , H01L23/498 , H01L25/065
CPC分类号: H01L23/562 , H01L23/16 , H01L23/3185 , H01L23/3675 , H01L23/49838 , H01L24/16 , H01L25/0652 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/18161 , H01L2924/3511
摘要: A semiconductor package includes a substrate including a wiring, a semiconductor chip structure on the substrate, and electrically connected to the wiring, an underfill resin in a space between the substrate and the semiconductor chip structure, and a stiffener surrounding the semiconductor chip structure, on the substrate, wherein the stiffener includes a conductive frame having a cavity and an insulating filler in the cavity.
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公开(公告)号:US12057363B2
公开(公告)日:2024-08-06
申请号:US17462458
申请日:2021-08-31
发明人: Po-Chen Lai , Ming-Chih Yew , Po-Yao Lin , Chin-Hua Wang , Shin-Puu Jeng
IPC分类号: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/14 , H01L23/29 , H01L23/498 , H01L25/065
CPC分类号: H01L23/3185 , H01L21/565 , H01L23/145 , H01L23/293 , H01L23/3192 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L2224/32056 , H01L2224/32059 , H01L2224/32225 , H01L2224/73204 , H01L2924/1431 , H01L2924/1434 , H01L2924/1811 , H01L2924/1815 , H01L2924/182 , H01L2924/186 , H01L2924/35121
摘要: Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.
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