Transmitter complex- and real-valued in-phase and quadrature mismatch pre-compensators

    公开(公告)号:US11595239B2

    公开(公告)日:2023-02-28

    申请号:US17572614

    申请日:2022-01-10

    Abstract: An in-phase and quadrature mismatch compensator for a quadrature transmitter includes a delay element, a complex-valued filter and an adder. The delay element receives an input transmit signal and outputs a delayed transmit signal. The complex-valued filter receives the input transmit signal and outputs a selected part of a filtered output transmit signal. The adder adds the delayed transmit signal and the selected part of the filtered output transmit signal and outputs a pre-compensated transmit signal. In one embodiment, the selected part of the filtered output transmit signal includes the real part of the complex-valued output transmit signal. In another embodiment, the selected part of the filtered output transmit signal includes the imaginary part of the complex-valued output transmit signal. Two transmit real-valued compensators are also disclosed that combine the in-phase and quadrature signals before being filtered.

    Systems, methods, and apparatus for combined power control of multiple transmit paths

    公开(公告)号:US11496969B2

    公开(公告)日:2022-11-08

    申请号:US17222979

    申请日:2021-04-05

    Abstract: A method of controlling power in a transmission system may include determining a first transmit power of a first transmit path, determining a second transmit power of a second transmit path, and controlling the first transmit path and the second transmit path based on a combination of the first transmit power and the second transmit power. The combination of the first transmit power and the second transmit power may include a sum of the first transmit power and the second transmit power. Controlling the first transmit path and the second transmit path may include determining a first effective power target for the first transmit path based on the first transmit power and the second transmit power, and determining a second effective power target for the second transmit path based on the first transmit power and the second transmit power.

    Transmitter complex- and real-valued in-phase and quadrature mismatch pre-compensators

    公开(公告)号:US11223509B2

    公开(公告)日:2022-01-11

    申请号:US17070912

    申请日:2020-10-14

    Abstract: An in-phase and quadrature mismatch compensator for a quadrature transmitter includes a delay element, a complex-valued filter and an adder. The delay element receives an input transmit signal and outputs a delayed transmit signal. The complex-valued filter receives the input transmit signal and outputs a selected part of a filtered output transmit signal. The adder adds the delayed transmit signal and the selected part of the filtered output transmit signal and outputs a pre-compensated transmit signal. In one embodiment, the selected part of the filtered output transmit signal includes the real part of the complex-valued output transmit signal. In another embodiment, the selected part of the filtered output transmit signal includes the imaginary part of the complex-valued output transmit signal. Two transmit real-valued compensators are also disclosed that combine the in-phase and quadrature signals before being filtered.

    System and method for providing filter/mixer structure for OFDM signal separation

    公开(公告)号:US11184206B2

    公开(公告)日:2021-11-23

    申请号:US16842019

    申请日:2020-04-07

    Abstract: An apparatus includes a first mixer performing first mixing of an input signal with a digital carrier which rotates the input signal such that one end of a target bandwidth in the input signal is aligned with an edge of a first bandpass filter that performs a first filtering on the first mixed input signal; a second mixer performing a second mixing of the first filtered input signal with a digital carrier which rotates the first filtered input signal such that the opposite end of the target bandwidth is aligned with an edge of a passband of a second bandpass filter that performs a second filtering on the second mixed input signal; and a third mixer performing a third mixing on the second filtered input signal which rotates the second filtered input signal such that the target bandwidth returns to the target bandwidth prior to the first mixing.

    Efficient polyphase architecture for interpolator and decimator

    公开(公告)号:US10917122B2

    公开(公告)日:2021-02-09

    申请号:US16656971

    申请日:2019-10-18

    Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

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