On-die impedance calibration
    11.
    发明申请
    On-die impedance calibration 失效
    片内阻抗校准

    公开(公告)号:US20070013395A1

    公开(公告)日:2007-01-18

    申请号:US11166825

    申请日:2005-06-24

    IPC分类号: G01R31/02

    CPC分类号: G01R31/2853

    摘要: One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.

    摘要翻译: 一个示例性器件具有多个具有端接阻抗的引线和标准阻抗。 在终端阻抗中,主阻抗被布置为通过与根据相关联的主阻抗被校准的标准阻抗和从阻抗比较来校准。