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    Converter circuit and open-circuit detection method of the same
    2.
    发明授权
    Converter circuit and open-circuit detection method of the same 有权

    公开(公告)号：US09989586B2

    公开(公告)日：2018-06-05

    申请号：US14682122

    申请日：2015-04-09

    申请人： Delta Electronics (Shanghai) Co., Ltd.

    发明人： Liang Liu ,  Bo-Yu Pu ,  Yi Zhang ,  Hong-Jian Gan ,  Jian-Ping Ying

    IPC分类号： G01R31/3187 ,  G01R31/28 ,  H02M7/487 ,  G01R31/02 ,  H02M1/32

    CPC分类号： G01R31/2884 ,  G01R31/026 ,  G01R31/2853 ,  H02M1/32 ,  H02M7/487

    摘要： A converter circuit is provided. The converter circuit includes a capacitor module, bridge arms, a voltage measuring module and an open-circuit detection module. Each bridge arm is connected to the capacitor module in parallel and includes an upper arm and a lower bridge arm connected at a middle point. The voltage measuring module measures voltage differences between each two bridge arms. The open-circuit detection module transmits test impulse signals to the bridge arms to activate at least one upper-conducted bridge arm and at least one lower-conducted bridge arm. The open-circuit detection module retrieves the voltage differences of each pair of the upper-conducted and lower-conducted bridge arms to make comparison with a reference value to determine an operation state thereof, and makes comparison of the operation state determined according to the different groups of test impulse signals to determine whether the upper and the lower bridge arms are actually open circuit.

    KILL DIE SUBROUTINE AT PROBE FOR REDUCING PARAMETRIC FAILING DEVICES AT PACKAGE TEST
    6.
    发明申请
    KILL DIE SUBROUTINE AT PROBE FOR REDUCING PARAMETRIC FAILING DEVICES AT PACKAGE TEST 审中-公开

    公开(公告)号：US20180011138A1

    公开(公告)日：2018-01-11

    申请号：US15713111

    申请日：2017-09-22

    申请人： Texas Instruments Incorporated

    发明人： HOI HIN LOO ,  SOH YING SEAH

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2851 ,  G01R31/2853 ,  G01R31/287 ,  G01R31/2894

    摘要： A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

    Apparatus and methods for dynamic passive intermodulation distortion testing
    7.
    发明授权
    Apparatus and methods for dynamic passive intermodulation distortion testing 有权

    公开(公告)号：US09863987B2

    公开(公告)日：2018-01-09

    申请号：US15335733

    申请日：2016-10-27

    申请人： CommScope Italy S.r.l.

    发明人： Riccardo Massa ,  Vito Caggiano ,  Gianluca Ratti

    IPC分类号： G01R23/20 ,  G01N3/34 ,  G01R31/28

    CPC分类号： G01R23/20 ,  G01N3/34 ,  G01R31/2853

    摘要： A passive intermodulation (“PIM”) distortion test apparatus includes a housing, hammering elements disposed within the housing, each hammering element including a moveable striking member, a strike plate positioned above the hammering elements, where a bottom surface of the strike plate is positioned at a distance above the hammering elements such that the moveable striking members of the hammering elements impact the strike plate when moved into their activated positions, and a retaining member that is configured to hold a device under test on a top surface of the strike plate while a PIM distortion test is performed on the device under test.

    Kill die subroutine at probe for reducing parametric failing devices at package test
    10.
    发明授权
    Kill die subroutine at probe for reducing parametric failing devices at package test 有权

    公开(公告)号：US09772372B2

    公开(公告)日：2017-09-26

    申请号：US14168648

    申请日：2014-01-30

    申请人： Texas Instruments Incorporated

    发明人： Hoi Hin Loo ,  Soh Ying Seah

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2851 ,  G01R31/2853 ,  G01R31/287 ,  G01R31/2894

    摘要： A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.