Method of managing independent word line read operation in flash memory and related memory controller and storage device

    公开(公告)号:US12067247B2

    公开(公告)日:2024-08-20

    申请号:US18078077

    申请日:2022-12-08

    Inventor: Tzu-Yi Yang

    CPC classification number: G06F3/0613 G06F3/0659 G06F3/0679

    Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

    Method and apparatus for performing data access control of memory device with aid of predetermined command

    公开(公告)号:US12061800B2

    公开(公告)日:2024-08-13

    申请号:US17862428

    申请日:2022-07-12

    Inventor: Tzu-Yi Yang

    CPC classification number: G06F3/0622 G06F3/0637 G06F3/0679

    Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first migrate command, for migrating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; writing the first data at the first destination logical address; and controlling the memory device to make the first data at the first source logical address become invalid data.

    METHOD OF MANAGING INDEPENDENT WORD LINE READ OPERATION IN FLASH MEMORY AND RELATED MEMORY CONTROLLER AND STORAGE DEVICE

    公开(公告)号:US20240192856A1

    公开(公告)日:2024-06-13

    申请号:US18078077

    申请日:2022-12-08

    Inventor: Tzu-Yi Yang

    CPC classification number: G06F3/0613 G06F3/0659 G06F3/0679

    Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

    Method and apparatus for page validity management and related storage system

    公开(公告)号:US11580018B2

    公开(公告)日:2023-02-14

    申请号:US17239669

    申请日:2021-04-25

    Inventor: Tzu-Yi Yang

    Abstract: A method of performing a garbage collection operation on a source block includes: performing a plurality of partial page clean operations during a series of host write operations. Each partial clean operation includes: performing a validity check process within a partitioned searching range of the source block to obtain valid page information; and performing a page clean process according to the valid page information and a target clean page number to read valid pages indicated by the valid page information.

    Data storage device and data processing method

    公开(公告)号:US11347640B2

    公开(公告)日:2022-05-31

    申请号:US17080856

    申请日:2020-10-27

    Abstract: A data storage device includes a memory device and a memory controller. The memory controller is arranged to configure a plurality of first memory blocks to receive data from a host device. The first memory blocks form at least a first superblock. When an amount of data stored in the first memory blocks reaches a specific value, the memory controller moves the data from the first memory blocks to a plurality of second memory blocks in a predetermined procedure. The second memory blocks form at least a second superblock. The second superblock includes the second memory blocks located in different memory chips. The data stored in two adjacent logical pages in the first superblock is written in two second memory blocks located in different memory chips.

    Data storage device and data processing method

    公开(公告)号:US20210279170A1

    公开(公告)日:2021-09-09

    申请号:US17080856

    申请日:2020-10-27

    Abstract: A data storage device includes a memory device and a memory controller. The memory controller is arranged to configure a plurality of first memory blocks to receive data from a host device. The first memory blocks form at least a first superblock. When an amount of data stored in the first memory blocks reaches a specific value, the memory controller moves the data from the first memory blocks to a plurality of second memory blocks in a predetermined procedure. The second memory blocks form at least a second superblock. The second superblock includes the second memory blocks located in different memory chips. The data stored in two adjacent logical pages in the first superblock is written in two second memory blocks located in different memory chips.

    Data storage device and data processing method

    公开(公告)号:US20210278994A1

    公开(公告)日:2021-09-09

    申请号:US17079503

    申请日:2020-10-25

    Inventor: Tzu-Yi Yang

    Abstract: A data storage device includes a memory device and a memory controller. The memory controller configures a first memory block which is a TLC memory blocks as a data buffer, and accordingly configures a plurality of second memory blocks which are SLC memory blocks. The memory controller uses the first memory block to receive data and accordingly store same data in the second memory blocks as backup data. When an amount of available memory space of the first memory block is smaller than or equal to a predetermined amount, the memory controller determines whether any error has occurred in the data stored in the first memory block. When there is any error occurred in the data stored in the first memory block, the memory controller configures a third memory block and move the backup data stored in the second memory block to the third memory block.

    FLASH MEMORY CONTROLLER, FLASH MEMORY DEVICE, AND CORRESPONDING METHODS FOR REDUCING ERROR RATE OF DATA ACCESS

    公开(公告)号:US20240411482A1

    公开(公告)日:2024-12-12

    申请号:US18646740

    申请日:2024-04-25

    Inventor: Tzu-Yi Yang

    Abstract: A method used in a flash memory controller includes: using an error correction code (ECC) circuit to perform an ECC operation upon data of a block of a flash memory chip/die of a flash memory device to generate an ECC result; when the ECC result indicates a failure, storing an access task corresponding to the block into a specific buffer; and, controlling a voltage generator of the flash memory device through a specific communication interface to control at least one address decoder of the flash memory device to access the block of the flash memory chip/die again according to at least one threshold voltage level of the voltage generator after the access task has been temporarily stored in the specific buffer for a specific default time.

    Garbage collection operation management based on overall spare area

    公开(公告)号:US11809312B2

    公开(公告)日:2023-11-07

    申请号:US17206137

    申请日:2021-03-19

    Inventor: Tzu-Yi Yang

    CPC classification number: G06F12/0253 G06F12/0246 G06F2212/7205

    Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: calculating an overall spare area in a flash memory, which includes a spare area in a plurality of spare blocks in the flash memory and at least two of a spare area in one or more target blocks corresponding to writing of user data based on host write commands, a spare area in one or more destination blocks corresponding to writing of valid data based on the GC operation and a spare area in a source block corresponding to reading of valid data based on the GC operation; determining an adjustment factor according to the overall spare area; and performing the GC operation on the source block according to a GC-to-host base ratio and the adjustment factor.

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