公开(公告)号：US20210320624A1

公开(公告)日：2021-10-14

申请号：US16967745

申请日：2020-04-30

Applicant: SOUTHEAST UNIVERSITY

Inventor： Chao CHEN ,  Jun YANG ,  Xinning LIU

IPC: H03F1/02 ,  H03F1/56

Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.

公开(公告)号：US20210313975A1

公开(公告)日：2021-10-07

申请号：US16957724

申请日：2019-07-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Jun YANG ,  Longxing SHI

IPC: H03K5/14 ,  H03K5/131 ,  G04F10/00

Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

公开(公告)号：US20210089874A1

公开(公告)日：2021-03-25

申请号：US17112329

申请日：2020-12-04

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Boyang CHENG ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/04 ,  G06F1/3203

Abstract: It discloses an ultra-low power keyword spotting neural network circuit and a method for mapping data. A neural network model used is a depthwise separable convolutional neural network, of which a weight value and an intermediate activation value are both binarized during training, to obtain a lightweight neural network model with a small memory size and a small computation quantity. The circuit is designed on the basis of a data processing unit array, utilizes a memory module to memorize a weight parameter and intermediate data of a keyword spotting neural network, data control and accuracy configuration of the data processing unit array are completed by means of a control module and a data mapping module, and the data processing unit array performs a neural network computation with hybrid accuracy; and the method for mapping the data configures.