公开(公告)号：US20250067112A1

公开(公告)日：2025-02-27

申请号：US18818064

申请日：2024-08-28

Applicant: Nice North America LLC

Inventor： Darren Learmonth ,  Jari Niemela ,  Gerald Dillon ,  Mark C. Mattson

IPC: E05F15/668 ,  E05F15/603 ,  E05F15/70 ,  E05F15/77 ,  G01R31/392 ,  G06F1/3203 ,  H02J9/06

Abstract: In one aspect, a garage door opener system includes a battery configured to be charged by a power source, a controller coupled to the battery, the controller configured to operate a motor that is powered only by the battery, at least one sensor coupled to the motor and the controller, the at least one sensor generating sensor data, and a battery monitoring system coupled to the battery, the controller, and the least one sensor, the battery monitoring system configured to monitor a power consumption of the battery and a state of the battery, and to update an operation configuration of the controller based on historical power consumption of the battery, the state of the battery, and the sensor data.

公开(公告)号：US12235698B2

公开(公告)日：2025-02-25

申请号：US18205014

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yeon Jeon ,  Dae Hwan Kim ,  Young Hoon Lee

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/28 ,  G11C5/14 ,  G06F1/30 ,  G06F1/3203

Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

公开(公告)号：US12228988B2

公开(公告)日：2025-02-18

申请号：US18339436

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Alon Naveh

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/3203

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.

公开(公告)号：US12197266B2

公开(公告)日：2025-01-14

申请号：US17992406

申请日：2022-11-22

Applicant: GoPro, Inc.

Inventor： Alexis Lefebvre ,  Vincent Vacquerie

IPC: G06F1/00 ,  G06F1/10 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/3203

Abstract: Systems and methods are disclosed for dynamic power allocation for memory using multiple interleaving patterns. For example, a system may include a set of memory devices, including a first subset and a second subset, and a memory management circuitry configured to translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode. The first and second interleaving patterns both map virtual addresses in a first range exclusively to memory devices in the first subset. The first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset. The second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.

公开(公告)号：US12164105B2

公开(公告)日：2024-12-10

申请号：US18137295

申请日：2023-04-20

Applicant: Snap Inc.

Inventor： Alex Bamberger ,  Peter Brook ,  Nicolas Dahlquist ,  Matthew Hanover ,  Russell Douglas Patton ,  Jonathan M Rodriguez, II

IPC: G02B27/01 ,  G02C11/00 ,  G06F1/16 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  H04N5/76 ,  H04N23/60 ,  H04N23/63 ,  H04N23/65 ,  H04N23/66 ,  H04N23/661

Abstract: One aspect disclosed is a method including determining a location from a positioning system receiver, determining, using a hardware processor and the location, that the location is approaching a path of direction of visual direction information, displaying the visual direction information on a display of a wearable device in response to the determining, determining, using the positioning system receiver, whether the turn of the visual direction information has been made, determining, by the hardware processor, a first period of time for display of the content data based on whether the turn of the visual direction information has been made, powering on the display and displaying, using the display, content data for the first period of time, turning off the display and the hardware processor following display of the content data.

公开(公告)号：US12141625B2

公开(公告)日：2024-11-12

申请号：US17395608

申请日：2021-08-06

Applicant: Dell Products, L.P.

Inventor： Ryan Nicholas Comer ,  Vivek Viswanathan Iyer ,  Daniel L. Hamlin

IPC: G06F9/50 ,  G06F1/3203 ,  G06F9/48 ,  G06N20/00

Abstract: Intelligent selection of optimization methods in heterogeneous environments is described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: identify a context; rank a plurality of optimization methods based upon the context; and execute at least a subset of the ranked optimization methods.

公开(公告)号：US12131174B2

公开(公告)日：2024-10-29

申请号：US17363634

申请日：2021-06-30

Applicant: International Business Machines Corporation

Inventor： Harish Bharti ,  Rajesh Kumar Saxena ,  Sandeep Sukhija ,  Deepak Bajaj

IPC: G06F9/455 ,  G06F1/3203 ,  G06F9/50 ,  G06F17/18 ,  H04L41/0895 ,  H04L41/50

CPC classification number: G06F9/45558 ,  G06F1/3203 ,  G06F9/5077 ,  G06F17/18 ,  H04L41/0895 ,  H04L41/50 ,  G06F2009/45595

Abstract: A system, method, and computer program product for determining “impact quantify measure-based” service chains cross interferences. The method includes quantifying the impact of one service chain on another service chain and to what extent so as facilitate making an informed decision whether to garner more resources and to fine tune the computational services for the service chain. There is further provided beforehand a certainty of required computational resources and the providing the impact or interferences details of one service chain on another helps in minimization of service quality degradation failures. The framework further runs a method step to apply a mutual convexity method on service chains to aid in forecasting cross interferences between chains and includes a step wherein, interferences between both dependent and independent service chain is calculated and provided. The provided interferences calculated result set will ensure while provisioning of virtual network functions doesn't consume energy excessively.

公开(公告)号：US12124310B2

公开(公告)日：2024-10-22

申请号：US18339827

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G09G3/06 ,  G06F1/3203 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30 ,  H04W52/02 ,  H04M1/72448

CPC classification number: G06F1/3209 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/0781 ,  G06F11/3062 ,  H04W52/0258 ,  H04M1/72448 ,  Y02D10/00 ,  Y02D30/70

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240345643A1

公开(公告)日：2024-10-17

申请号：US18753266

申请日：2024-06-25

Applicant: Wacom Co., Ltd.

Inventor： Shahrooz Shahparnia ,  Trond Jarle Pedersen ,  John Logan ,  Vemund Kval Bakken ,  Kishore Sundara-Rajan

IPC: G06F1/3203 ,  G06F3/0354 ,  G06F3/044

CPC classification number: G06F1/3203 ,  G06F3/03545 ,  G06F3/0441 ,  G06F3/0442

Abstract: In one embodiment, a stylus includes one or more electrodes and one or more computer-readable non-transitory storage media embodying first logic for transmitting signals wirelessly to a device through a touch-sensor of the device. The stylus has a first power mode in which components of the stylus for receiving signals from or transmitting signals to the device are powered off; a second power mode in which components of the stylus for receiving signals from the device are powered on at least periodically and components of the stylus for transmitting signals to the device are powered off; and a third power mode in which components of the stylus for transmitting signals to the device are powered on at least periodically. The media further embodies second logic for transitioning the stylus from one of the first, second, and third power modes to another one of the first, second, and third power modes.

公开(公告)号：US20240310893A1

公开(公告)日：2024-09-19

申请号：US18676855

申请日：2024-05-29

Applicant: SambaNova Systems, Inc.

Inventor： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/28 ,  G06F1/30 ,  G06F1/3203 ,  G06F9/445

CPC classification number: G06F1/28 ,  G06F9/44505 ,  G06F1/30 ,  G06F1/3203

Abstract: An integrated circuit (IC) comprises an array of power base units (PBUs) organized in rows and columns. The IC further includes an array-level power accumulator that includes a power estimation unit (PEU) and two or more column power accumulators (CPAs) coupled with the PEU and the PBUs via dedicated wiring. Additionally, a power clock management controller (PCMC) is linked to the array-level power accumulator. Notably, some CPAs are connected to the array-level power accumulator through dedicated wiring.