Abstract:
A target discovery manager associated with a target discovery layer is interposed between a host initiator and one or more discovery protocols. The target discovery manager maintains a list of target devices found by each of several target discovery protocols. For each discovered target device listed, the associated discovery protocols that discovered the target device are prioritized and coalesced into a single enumerated target device register. The target device register provides the host initiator with a single list of known target devices produced from multiple discovery protocols with the discovery protocols that independently discovered each device prioritized according to various parameters.
Abstract:
A method for handling input/output (I/O) commands in a storage system includes establishing first and second counters for counting unfinished I/O commands, and establishing a reference which is initially set to the first counter. The reference is periodically switched between the first counter and the second counter, and the switching interval is less than the I/O timeout value. Upon placing an I/O command into an I/O command queue, a copy of the current reference is made into an I/O specific control block and the current referenced counter is incremented. Upon finishing of an I/O command, the counter referenced by the I/O specific control block is decremented and the I/O command is removed from the I/O command queue. When switching the reference, a problem is detected in the event that the counter being switched to is above a predetermined threshold. Upon detection of a problem, a more explicit I/O check is conducted.
Abstract:
A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.