公开(公告)号：US20160112055A1

公开(公告)日：2016-04-21

申请号：US14868785

申请日：2015-09-29

Applicant: Texas Instruments Incorporated

Inventor： Peeyoosh Nitin Mirajkar ,  Jagdish Chand Goyal ,  Sankaran Aniruddhan

IPC: H03L7/095 ,  H03L7/091 ,  H03L7/093 ,  H03L7/089

CPC classification number: H03L7/095 ,  H03L7/089 ,  H03L7/1072 ,  H03L7/1077

Abstract: Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.

Abstract translation: 所描述的示例包括控制锁相环（PLL）或其他锁定电路的锁定时间的电路和方法，其中相位频率检测器（PFD）电路从第一模式切换以向电荷泵提供控制输入信号作为 脉冲信号具有对应于参考时钟信号和反馈时钟信号之间的相位差的脉冲宽度到第二模式，以响应于检测到的周期滑移条件将控制输入信号保持在恒定值一段预定时间以增强环路 在频率转换期间过滤电流，以减少锁定电路的锁定时间。