公开(公告)号：US20230228814A1

公开(公告)日：2023-07-20

申请号：US18123406

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

公开(公告)号：US20230194603A1

公开(公告)日：2023-06-22

申请号：US18108720

申请日：2023-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

公开(公告)号：US20230160958A1

公开(公告)日：2023-05-25

申请号：US18094522

申请日：2023-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/3183

CPC classification number: G01R31/31723 ,  G01R31/3177 ,  G01R31/318594 ,  G01R31/318572 ,  G01R31/318558 ,  G01R31/2896 ,  G01R31/318552 ,  G01R31/3183 ,  G01R31/318513 ,  G01R31/318555 ,  G01R31/31724 ,  G01R31/31727

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

公开(公告)号：US11635464B2

公开(公告)日：2023-04-25

申请号：US17665616

申请日：2022-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

公开(公告)号：US11609269B2

公开(公告)日：2023-03-21

申请号：US17406320

申请日：2021-08-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

公开(公告)号：US11585852B2

公开(公告)日：2023-02-21

申请号：US17692057

申请日：2022-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G06F11/26 ,  G01R31/317 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56 ,  H01L27/12

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

公开(公告)号：US11585851B2

公开(公告)日：2023-02-21

申请号：US17491654

申请日：2021-10-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317 ,  H01L23/00

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

公开(公告)号：US11579193B2

公开(公告)日：2023-02-14

申请号：US17462572

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

公开(公告)号：US11519959B2

公开(公告)日：2022-12-06

申请号：US16950030

申请日：2020-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

公开(公告)号：US11428736B2

公开(公告)日：2022-08-30

申请号：US17323666

申请日：2021-05-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.