Calibration of parametric error of digital-to-time converters

    公开(公告)号:US11632116B2

    公开(公告)日:2023-04-18

    申请号:US17573323

    申请日:2022-01-11

    Abstract: In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

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