公开(公告)号：US20220140129A1

公开(公告)日：2022-05-05

申请号：US17576142

申请日：2022-01-14

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/74 ,  H01L21/762 ,  H01L21/765

Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

公开(公告)号：US10978559B1

公开(公告)日：2021-04-13

申请号：US16983585

申请日：2020-08-03

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

公开(公告)号：US20210074839A1

公开(公告)日：2021-03-11

申请号：US16563366

申请日：2019-09-06

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/74 ,  H01L21/762 ,  H01L21/765 ,  H01L29/66

Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

公开(公告)号：US10886418B2

公开(公告)日：2021-01-05

申请号：US16281626

申请日：2019-02-21

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie

IPC: H01L29/80 ,  H01L31/112 ,  H01L29/808 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40

Abstract: An IC with a split-gate transistor includes a substrate doped the second conductivity type having a semiconductor surface layer doped the first conductivity type. The transistor includes a first doped region formed as an annulus, a second doped region including under the first doped region, and a third doped region under the second doped region, all coupled together and doped the second conductivity type. A fourth doped region doped the first conductivity type is above the third doped region. A fifth doped region doped the first conductivity type is outside the annulus. Sixth doped regions doped the first conductivity type include a first sixth doped region surrounded by the annulus in the semiconductor surface layer and a second sixth doped region in the fifth doped region. Field oxide includes a field oxide portion between the fifth and the first doped region. A field plate is on the field oxide portion.