公开(公告)号：US09812191B1

公开(公告)日：2017-11-07

申请号：US15279944

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Avinash Chander ,  Yen-Huei Chen

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C29/12015

Abstract: A memory device includes: a memory array comprising a first plurality of bit cells arranged along a first column; and a negative bit line (NBL) circuit, coupled to the memory array. The NBL circuit includes: a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.