公开(公告)号：US10991423B2

公开(公告)日：2021-04-27

申请号：US16583039

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C5/06 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US20200020392A1

公开(公告)日：2020-01-16

申请号：US16583060

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  G11C11/412 ,  G11C8/16 ,  G11C7/10

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US10157666B2

公开(公告)日：2018-12-18

申请号：US15871484

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C8/00 ,  G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US20200020391A1

公开(公告)日：2020-01-16

申请号：US16583039

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  G11C11/412 ,  G11C8/16 ,  G11C7/10

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US20180137910A1

公开(公告)日：2018-05-17

申请号：US15871484

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  G11C11/412 ,  G11C8/16 ,  G11C7/10 ,  H01L23/522 ,  H01L27/11 ,  H01L23/528

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104 ,  H01L28/00

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US20170186750A1

公开(公告)日：2017-06-29

申请号：US15384373

申请日：2016-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Yen-Huei Chen ,  Avinash Chander

IPC: H01L27/105 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/1052 ,  G11C5/025 ,  G11C5/063 ,  G11C7/12 ,  G11C8/08 ,  G11C8/16 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528

Abstract: An interconnect structure includes a lower interconnect layer, an intermediate interconnect layer, and an upper interconnect layer. First and second conductive lines in the lower interconnect layer extend generally in a first direction over a memory array region, and additional lower conductive lines in the lower interconnect layer extend generally in the first direction over a peripheral region. A first plurality of conductive line segments in the intermediate interconnect layer extend generally in the first direction over the memory array region, and additional intermediate conductive line segments in the intermediate interconnect layer extend generally in a second, perpendicular direction over the peripheral region. A second plurality of conductive line segments in the upper interconnect layer extend generally in the first direction over the memory array region, and additional upper conductive line segments in the upper interconnect layer extend generally in the first direction over the peripheral region.

公开(公告)号：US20170186483A1

公开(公告)日：2017-06-29

申请号：US15388991

申请日：2016-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104 ,  H01L28/00

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US10790015B2

公开(公告)日：2020-09-29

申请号：US16583060

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C5/06 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US20190108875A1

公开(公告)日：2019-04-11

申请号：US16211640

申请日：2018-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  G11C11/412 ,  G11C8/16 ,  G11C7/10 ,  H01L23/522 ,  H01L27/11 ,  H01L23/528 ,  H01L49/02

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US09928899B2

公开(公告)日：2018-03-27

申请号：US15388991

申请日：2016-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C8/00 ,  G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104 ,  H01L28/00

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.