公开(公告)号：US09245887B2

公开(公告)日：2016-01-26

申请号：US13955796

申请日：2013-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Hui-Zhong Zhuang ,  Shang-Chih Hsieh ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/092 ,  H01L27/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/092 ,  G06F17/5068 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.

Abstract translation: 集成电路布局包括第一有源区，第二有源区，第一PODE（OD边缘上的poly），第二PODE，第一晶体管和第二晶体管。 在第一有源区上的第一晶体管包括栅电极，源极区和漏极区。 在第二有源区上的第二晶体管包括栅电极，源极区和漏极区。 第一有源区和第二有源区相邻并且彼此电断开。 第一PODE和第二PODE位于第一有源区和第二有源区的相邻相邻边缘上。 第一和第二晶体管的源极区分别与第一PODE和第二PODE相邻。 第一PODE和第二PODE夹在第一晶体管和第二晶体管的源极区之间。