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公开(公告)号：US12081215B2
公开(公告)日：2024-09-03
申请号：US18333284
申请日：2023-06-12
发明人： Yu-Lun Ou , Ji-Yung Lin , Yung-Chen Chien , Ruei-Wun Sun , Wei-Hsiang Ma , Jerry Chang Jui Kao , Shang-Chih Hsieh , Lee-Chung Lu
IPC分类号： H03K3/037 , H03K19/0185
CPC分类号： H03K19/018521 , H03K3/037
摘要： A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
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公开(公告)号：US20240037309A1
公开(公告)日：2024-02-01
申请号：US18345389
申请日：2023-06-30
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Jian-Sing Li , Wei-Hsiang Ma , Yi-Hsun Chen , Cheok-Kei Lei
IPC分类号： G06F30/392 , G06F30/347 , G06F30/39 , H01L27/02
CPC分类号： G06F30/392 , G06F30/347 , G06F30/39 , H01L27/0207
摘要： A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
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公开(公告)号：US10664565B2
公开(公告)日：2020-05-26
申请号：US15936712
申请日：2018-03-27
发明人： Chi-Lin Liu , Sheng-Hsiung Chen , Jerry Chang-Jui Kao , Fong-Yuan Chang , Lee-Chung Lu , Shang-Chih Hsieh , Wei-Hsiang Ma
IPC分类号： G06F17/50
摘要： A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.
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公开(公告)号：US10380306B2
公开(公告)日：2019-08-13
申请号：US15356817
申请日：2016-11-21
摘要： An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.
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公开(公告)号：US09584099B2
公开(公告)日：2017-02-28
申请号：US14539407
申请日：2014-11-12
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Lee-Chung Lu , Chang-Yu Wu
IPC分类号： H03K3/356 , H03K3/037 , G01R31/3185
CPC分类号： H03K3/356104 , G01R31/318541 , H03K3/037 , H03K3/356121
摘要： A flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal.
摘要翻译： 触发器电路包括第一锁存器，第二锁存器和触发器级。 第一锁存器被配置为基于第一锁存器输入信号和时钟信号来设置第一锁存器输出信号。 第二锁存器被配置为基于第二锁存器输入信号和时钟信号来设置第二锁存器输出信号。 触发级被配置为基于第一锁存器输出信号产生第二锁存器输入信号。 触发级被配置为基于第一锁存器输出信号和第二锁存器输出信号使第二输入信号具有不同的电压摆幅。
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公开(公告)号：US11152923B2
公开(公告)日：2021-10-19
申请号：US16538221
申请日：2019-08-12
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Lee-Chung Lu , Chang-Yu Wu
IPC分类号： H03K3/356 , G01R31/3185 , H03K3/037
摘要： A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on at least a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have a first voltage swing or a second voltage swing based on the first output signal and the second output signal. The first voltage swing is different from the second voltage swing.
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公开(公告)号：US09356583B2
公开(公告)日：2016-05-31
申请号：US14472937
申请日：2014-08-29
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Lee-Chung Lu , Chang-Yu Wu
CPC分类号： H03K3/356104 , G01R31/318541 , H03K3/037 , H03K3/356121
摘要： A flip-flop circuit includes a first latch, a trigger stage and a second latch. The first latch is configured to latch a selected signal in response to a first state of a clock signal, and provide a first output signal. The trigger stage receives the clock signal and the first output signal to provide a trigger signal. The trigger signal does not toggle as the clock signal transits. The second latch is configured to latch the trigger signal in response to a second state of the clock signal, and provide a second output signal. The first state and the second state of the clock signal are complementary to each other.
摘要翻译： 触发器电路包括第一锁存器，触发级和第二锁存器。 第一锁存器被配置为响应于时钟信号的第一状态来锁存所选择的信号，并且提供第一输出信号。 触发级接收时钟信号和第一输出信号以提供触发信号。 随着时钟信号的转换，触发信号不会切换。 第二锁存器被配置为响应于时钟信号的第二状态来锁存触发信号，并提供第二输出信号。 时钟信号的第一状态和第二状态彼此互补。
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公开(公告)号：US12074603B1
公开(公告)日：2024-08-27
申请号：US18313384
申请日：2023-05-08
IPC分类号： H03K3/037 , H03K3/3562
CPC分类号： H03K3/0372 , H03K3/0375 , H03K3/35625
摘要： The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.
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公开(公告)号：US11983479B2
公开(公告)日：2024-05-14
申请号：US17885118
申请日：2022-08-10
发明人： Jung-Chan Yang , Ting-Wei Chiang , Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Lee-Chung Lu , Li-Chun Tien , Meng-Hung Shen , Shang-Chih Hsieh , Chi-Yu Lu
IPC分类号： G06F30/394 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/118
CPC分类号： G06F30/394 , H01L23/5226 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2027/11887
摘要： A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
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公开(公告)号：US11942945B2
公开(公告)日：2024-03-26
申请号：US17815156
申请日：2022-07-26
发明人： Huaixin Xian , Qingchao Meng , Yang Zhou , Shang-Chih Hsieh
IPC分类号： H01L27/105 , H01L29/02 , H01L29/06 , H01L29/10 , H01L29/417 , H03K3/037 , H03K3/288 , H03K3/289 , H03K3/356 , H03K3/3562
CPC分类号： H03K3/0372 , H01L27/105 , H01L29/02 , H01L29/06 , H01L29/1075 , H01L29/41725 , H03K3/288 , H03K3/289 , H03K3/356017 , H03K3/356104 , H03K3/356113 , H03K3/356147 , H03K3/3562 , H03K3/35625
摘要： A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.
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