公开(公告)号：US06868514B2

公开(公告)日：2005-03-15

申请号：US09890858

申请日：2000-12-06

申请人： Kazuo Kubo ,  Hideo Yoshida ,  Hiroshi Ichibangase ,  Hidenori Taga ,  Eiichi Shibano ,  Tadami Yasuda

发明人： Kazuo Kubo ,  Hideo Yoshida ,  Hiroshi Ichibangase ,  Hidenori Taga ,  Eiichi Shibano ,  Tadami Yasuda

IPC分类号： H03M13/15 ,  H03M13/27 ,  H03M13/29 ,  H04J3/00 ,  H04L1/00

CPC分类号： H03M13/2921 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2721 ,  H03M13/6561

摘要： In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is returned to the original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct errors in the information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit 37.

摘要翻译： 在FEC帧结构方法和FEC多路复用器中，由第一交织电路32改变信息的顺序，由RS（239,223）编码电路33生成第一纠错码，顺序返回到 通过第一去交织电路34的原始顺序，并且由RS（255,239）编码装置5产生第二纠错码。第二纠错码由RS（255,239）解码电路11解码以校正错误 在信息中，通过第二交错电路35改变信息的顺序，由RS（239,223）解码电路36对第一纠错码进行解码，以校正信息中的残差，并将顺序返回到 通过第二去交织电路37的原始顺序。

公开(公告)号：US5287389A

公开(公告)日：1994-02-15

申请号：US765149

申请日：1991-09-25

申请人： Hiroshi Ichibangase ,  Kiwami Matsushita

发明人： Hiroshi Ichibangase ,  Kiwami Matsushita

IPC分类号： H04J3/02 ,  H04J3/06 ,  H04L7/08

CPC分类号： H04J3/0608

摘要： A frame alignment circuit is disclosed which includes multi-stage dividing counters and multi-stage line demultiplexing circuits. The shift pulse for frame synchronizing is converted to the width of the first divided clock signal and applied to the first dividing counter. Accordingly, the frame synchronization is easily established by demultiplexing the high rate multiplexed coded signal even if the number of demultiplexing line is increased.

摘要翻译： 公开了一种帧对准电路，其包括多级分频计数器和多级线路解复用电路。 用于帧同步的移位脉冲被转换为第一分频时钟信号的宽度并施加到第一分频计数器。 因此，即使解复用线的数量增加，也可以通过对高速复用编码信号进行解复用来容易地建立帧同步。