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    DMA transfer from a storage unit to a host using at least two transfer rates and cyclic error detection
    11.
    发明授权
    DMA transfer from a storage unit to a host using at least two transfer rates and cyclic error detection 失效
    使用至少两个传输速率和循环错误检测从存储单元DMA传输到主机

    公开(公告)号：US06209046B1

    公开(公告)日：2001-03-27

    申请号：US09121944

    申请日：1998-07-24

    申请人： Masahiko Sato ,  Toshio Kakihara ,  Atsushi Kanamaru ,  Hiroshi Oshikawa ,  Hideo Asano

    发明人： Masahiko Sato ,  Toshio Kakihara ,  Atsushi Kanamaru ,  Hiroshi Oshikawa ,  Hideo Asano

    IPC分类号： G06F1338

    CPC分类号： G06F3/0613 ,  G06F3/0653 ,  G06F3/0676 ,  G06F13/385

    摘要： Methods and apparatus are described for a data transfer unit between a storage unit and a host, wherein a slower data transfer rate is established when a predetermined error is detected. In one embodiment the cyclicity of the error occurrence calculated and a wait is inserted between data to avoid transferring data at the calculated cyclicity point of the detected error. Optionally the data transfer unit may return the data transfer rate to the original data transfer rate or state after a predetermined time has elapsed, after a predetermined number of commands have been received, after a predetermined amount of data have been transferred, or by combination of these.

    摘要翻译： 对于存储单元和主机之间的数据传送单元描述了方法和装置，其中当检测到预定的错误时建立较慢的数据传输速率。 在一个实施例中，计算的错误发生的周期性和等待被插入在数据之间以避免在所检测的错误的计算的循环点处传送数据。 可选地，数据传送单元可以在经过预定数量的命令已经被传送了预定数量的命令之后经过预定时间过去之后将数据传输速率返回到原始数据传输速率或状态， 这些。