公开(公告)号：US20230064481A1

公开(公告)日：2023-03-02

申请号：US17463341

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Tarkesh PANDE ,  Rishabh GARG ,  Pramod Kumar SWAMI ,  Kumar DESAPPAN ,  Aishwarya DUBEY

IPC: G06N20/00 ,  G06K9/62

Abstract: An electronic device, comprising one or more processors, wherein the one or more processors are configured to execute instructions causing the one or more processors to: receive a machine learning (ML) model and execution information associated with the ML model, wherein the execution information including first execution data indicating how to execute the ML model optimized based on a first performance criterion, and second execution data execution data indicating how to execute the ML model optimized based on a second performance criteria, the second performance criterion different from the first performance criteria; execute the ML model based on the first execution data; determine to execute the ML model based on the second execution data; and execute the ML model based on the second execution data.

公开(公告)号：US20220012635A1

公开(公告)日：2022-01-13

申请号：US17327869

申请日：2021-05-24

Applicant: Texas Instruments Incorporated

Inventor： Rishabh GARG ,  Pramod Kumar SWAMI ,  Kumar DESAPPAN ,  Anshu JAIN

IPC: G06N20/00 ,  G06K9/62 ,  G06F11/30

Abstract: Techniques for enhancing machine learning (ML) model execution. The technique includes determining an amount of memory used to process layers of a machine learning network having multiple layers, smoothing the amount of memory used to process the layers of the machine learning network based on a number of layers, identifying change layers where the smoothed amount of memory used changes more than a memory change threshold amount, grouping the layers of the machine learning network into a first layer grouping based on the identified change layers, and outputting the first layer grouping.

公开(公告)号：US20210256293A1

公开(公告)日：2021-08-19

申请号：US17149474

申请日：2021-01-14

Applicant: Texas Instruments Incorporated

Inventor： Deepak Kumar PODDAR ,  Soyeb NAGORI ,  Hrushikesh Tukaram GARUD ,  Pramod Kumar SWAMI

IPC: G06K9/62 ,  G06F9/50 ,  G06F7/523 ,  G06F17/16

Abstract: A matching accelerator in the form of a hardware accelerator configured to perform matrix multiplication and/or additional operations is used to optimize keypoint matching. An SSE calculation may be determined by utilizing the matching accelerator to perform matrix multiplication to obtain a cost matrix for two sets of keypoint descriptors from two images. The hardware accelerator may determine a best cost calculation for each keypoint in each direction, which is utilized to perform keypoint matching.