ALIASED MODE FOR CACHE CONTROLLER

    公开(公告)号:US20210365374A1

    公开(公告)日:2021-11-25

    申请号:US16882344

    申请日:2020-05-22

    Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

    VIDEO OBJECT DETECTION
    2.
    发明申请

    公开(公告)号:US20190295262A1

    公开(公告)日:2019-09-26

    申请号:US16157861

    申请日:2018-10-11

    Abstract: A method for video object detection includes detecting an object in a first video frame, and selecting a first interest point and a second interest point of the object. The first interest point is in a first region of interest located at a first corner of a box surrounding the object. The second interest point is in a second region of interest located at a second corner of the box. The second corner is diagonally opposite the first corner. A first optical flow of the first interest point and a second optical flow of the second interest point are determined. A location of the object in a second video frame is estimated by determining, in the second video frame, a location of the first interest point based on the first optical flow and a location of the second interest point based on the second optical flow.

    ALIASED MODE FOR CACHE CONTROLLER

    公开(公告)号:US20220327055A1

    公开(公告)日:2022-10-13

    申请号:US17847131

    申请日:2022-06-22

    Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

    VIDEO OBJECT DETECTION
    8.
    发明申请

    公开(公告)号:US20210056710A1

    公开(公告)日:2021-02-25

    申请号:US17093681

    申请日:2020-11-10

    Abstract: A method for video object detection includes detecting an object in a first video frame, and selecting a first interest point and a second interest point of the object. The first interest point is in a first region of interest located at a first corner of a box surrounding the object. The second interest point is in a second region of interest located at a second corner of the box. The second corner is diagonally opposite the first corner. A first optical flow of the first interest point and a second optical flow of the second interest point are determined. A location of the object in a second video frame is estimated by determining, in the second video frame, a location of the first interest point based on the first optical flow and a location of the second interest point based on the second optical flow.

    SUPER-TILING IN NEURAL NETWORK PROCESSING TO ENABLING ANALYTICS AT LOWER MEMORY SPEED

    公开(公告)号:US20200272892A1

    公开(公告)日:2020-08-27

    申请号:US16797871

    申请日:2020-02-21

    Abstract: Techniques including receiving a first set of values for processing by a machine learning (ML) network, storing a first portion of the first set of values in an on-chip memory, processing the first portion of the first set of values in a first layer of the ML network to generate a second portion of a second set of values, overwriting the stored first portion with the generated second portion, processing the second portion in a second layer of the ML network to generate a third portion of a third set of values, storing the third portion, repeating the steps of storing the first portion, processing the first portion, overwriting the stored first portion, processing the second portion, and storing the third portion for a fourth portion of the first set of values until all portions of the first set of values are processed to generate the third set of values.

    FEATURE POINT IDENTIFICATION IN SPARSE OPTICAL FLOW BASED TRACKING IN A COMPUTER VISION SYSTEM

    公开(公告)号:US20240153105A1

    公开(公告)日:2024-05-09

    申请号:US18414772

    申请日:2024-01-17

    Abstract: A method for sparse optical flow based tracking in a computer vision system is provided that includes detecting feature points in a frame captured by a monocular camera in the computer vision system to generate a plurality of detected feature points, generating a binary image indicating locations of the detected feature points with a bit value of one, wherein all other locations in the binary image have a bit value of zero, generating another binary image indicating neighborhoods of currently tracked points, wherein locations of the neighborhoods in the binary image have a bit value of zero and all other locations in the binary image have a bit value of one, and performing a binary AND of the two binary images to generate another binary image, wherein locations in the binary image having a bit value of one indicate new feature points detected in the frame.

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