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公开(公告)号：US5247471A
公开(公告)日：1993-09-21
申请号：US807002
申请日：1991-12-13
摘要： In a hardware floating point adder, each operand exponent is logically divided into fields. The corresponding fields of each exponent are input to a separate shift logic circuit which determines a relative amount to shift the operand mantissa without reference to any carry bit from a lower order field. Both mantissas are potentially shifted, each by one or more shift logic circuit outputs, making it possible to perform some of the shifts simultaneously. Using 11 bit exponents in accordance with ANSI/IEEE Standard 754-1985, double format for 64-bit numbers, operand registers are logically divided into: field #3, consisting the lowest two order bits; field #2 consisting of the next lowest two order bits after the first two; and field #1 consisting of the highest 7 order bits. The shift logic circuit for field #3 shifts and Operand A mantissa, right or left, 0, 1, 2 or 3 bits. The shift logic circuit for field #2 simultaneously shifts an Operand B mantissa, right or left, 0, 4, 8 or 12 bits. The shift logic circuits for field #1 shifts and Operand B mantissa, right or left, 0, 16, 32, 48 or 64 bits; this shift is performed after the shift from field #2. The cumulative shifts performed above effect a relative shift of the two mantissas by the correct amount. The mantissas are then added/subtracted in the normal manner, and shift adjusted after the addition/subtraction.
摘要翻译： 在硬件浮点加法器中，每个操作数指数在逻辑上分为字段。 每个指数的相应字段被输入到单独的移位逻辑电路，该移位逻辑电路确定相对量以移位操作数尾数，而不参考来自低阶字段的任何进位位。 两个尾数都可能由一个或多个移位逻辑电路输出移位，使得可以同时执行一些移位。 根据ANSI / IEEE标准754-1985使用11位指数，64位数字的双格式，操作数寄存器在逻辑上分为：字段＃3，包括最低两位; 字段＃2由前两个之后的下一个最低二位组成; 和由最高7位位组成的场＃1。 字段＃3的移位逻辑电路将操作数A的尾数向右或向左移位0,1,2或3位。 字段＃2的移位逻辑电路同时移位操作数B尾数，右或左，0,4,8或12位。 字段＃1的移位逻辑电路移位和操作数B尾数，左或右，0,16,32,48或64位; 这种偏移在从场＃2移位之后进行。 以上执行的累积移动会使两个尾数的相对移动达到正确的数量。 然后以常规方式添加/减去尾数，并在加/减之后进行移位调整。
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公开(公告)号：US5117384A
公开(公告)日：1992-05-26
申请号：US702341
申请日：1991-04-03
申请人： Robert A. Drehmel , Scott A. Hilker
发明人： Robert A. Drehmel , Scott A. Hilker
CPC分类号： G06F7/485
摘要： An apparatus and method for determining the difference between two exponents of two floating point numbers is disclosed. The exponent of each number is split into two portions. A high portion contains the most significant bits and a low portion contains the least significant bits. The number of bits in the low portion is related to the number of bits in the fraction portion of each floating point number. To determine differences that require a shift in one of the exponenets, one of the differences between the low portions of the exponents is selected based upon which of several conditions are found with respect to the difference between the high portion. Advantageously, a set of adders which are as wide as the number of bits in the low portion of each exponent are used.
摘要翻译： 公开了一种用于确定两个浮点数的两个指数之间的差异的装置和方法。 每个数字的指数分为两部分。 高部分包含最高有效位，而低部分包含最低有效位。 低部分中的比特数与每个浮点数的分数部分中的比特数有关。 为了确定需要在其中一个指数中移位的差异，基于相对于高部分之间的差异找到几个条件中的哪一个来选择指数的低部分之间的差异之一。 有利地，使用与每个指数的低部分中的位数一样宽的一组加法器。
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