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1.发明申请ARITHMETIC PROCESSING UNIT THAT PERFORMS MULTIPLY AND MULTIPLY-ADD OPERATIONS WITH SATURATION AND METHOD THEREFOR 有权具有饱和度的多项式和多项式运算的算术处理单元及其方法公开(公告)号：US20100306301A1
公开(公告)日：2010-12-02
申请号：US12472715
申请日：2009-05-27
申请人： Kevin A. Hurd , Scott A. Hilker
发明人： Kevin A. Hurd , Scott A. Hilker
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/49921 , G06F7/53 , G06F7/5443
摘要： Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.
摘要翻译： 形成表示第一和第二操作数的乘积的和和进位信号。 形成具有由第一和第二操作数的乘积的符号确定的值的偏置信号。 基于和信号，进位信号，符号扩展加数和偏置信号的相加来提供输出信号。 基于产品的符号和输出信号的符号，选择输出信号的一部分，饱和最小值或饱和最大值作为最终结果。
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公开(公告)号：US5247471A
公开(公告)日：1993-09-21
申请号：US807002
申请日：1991-12-13
摘要： In a hardware floating point adder, each operand exponent is logically divided into fields. The corresponding fields of each exponent are input to a separate shift logic circuit which determines a relative amount to shift the operand mantissa without reference to any carry bit from a lower order field. Both mantissas are potentially shifted, each by one or more shift logic circuit outputs, making it possible to perform some of the shifts simultaneously. Using 11 bit exponents in accordance with ANSI/IEEE Standard 754-1985, double format for 64-bit numbers, operand registers are logically divided into: field #3, consisting the lowest two order bits; field #2 consisting of the next lowest two order bits after the first two; and field #1 consisting of the highest 7 order bits. The shift logic circuit for field #3 shifts and Operand A mantissa, right or left, 0, 1, 2 or 3 bits. The shift logic circuit for field #2 simultaneously shifts an Operand B mantissa, right or left, 0, 4, 8 or 12 bits. The shift logic circuits for field #1 shifts and Operand B mantissa, right or left, 0, 16, 32, 48 or 64 bits; this shift is performed after the shift from field #2. The cumulative shifts performed above effect a relative shift of the two mantissas by the correct amount. The mantissas are then added/subtracted in the normal manner, and shift adjusted after the addition/subtraction.
摘要翻译： 在硬件浮点加法器中，每个操作数指数在逻辑上分为字段。 每个指数的相应字段被输入到单独的移位逻辑电路，该移位逻辑电路确定相对量以移位操作数尾数，而不参考来自低阶字段的任何进位位。 两个尾数都可能由一个或多个移位逻辑电路输出移位，使得可以同时执行一些移位。 根据ANSI / IEEE标准754-1985使用11位指数，64位数字的双格式，操作数寄存器在逻辑上分为：字段＃3，包括最低两位; 字段＃2由前两个之后的下一个最低二位组成; 和由最高7位位组成的场＃1。 字段＃3的移位逻辑电路将操作数A的尾数向右或向左移位0,1,2或3位。 字段＃2的移位逻辑电路同时移位操作数B尾数，右或左，0,4,8或12位。 字段＃1的移位逻辑电路移位和操作数B尾数，左或右，0,16,32,48或64位; 这种偏移在从场＃2移位之后进行。 以上执行的累积移动会使两个尾数的相对移动达到正确的数量。 然后以常规方式添加/减去尾数，并在加/减之后进行移位调整。
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公开(公告)号：USH1222H
公开(公告)日：1993-08-03
申请号：US814934
申请日：1991-12-30
申请人： Jeffrey D. Brown , Roy R. Faget , Scott A. Hilker
发明人： Jeffrey D. Brown , Roy R. Faget , Scott A. Hilker
CPC分类号： G06F7/483 , G06F7/49952
摘要： An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.
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公开(公告)号：US5117384A
公开(公告)日：1992-05-26
申请号：US702341
申请日：1991-04-03
申请人： Robert A. Drehmel , Scott A. Hilker
发明人： Robert A. Drehmel , Scott A. Hilker
CPC分类号： G06F7/485
摘要： An apparatus and method for determining the difference between two exponents of two floating point numbers is disclosed. The exponent of each number is split into two portions. A high portion contains the most significant bits and a low portion contains the least significant bits. The number of bits in the low portion is related to the number of bits in the fraction portion of each floating point number. To determine differences that require a shift in one of the exponenets, one of the differences between the low portions of the exponents is selected based upon which of several conditions are found with respect to the difference between the high portion. Advantageously, a set of adders which are as wide as the number of bits in the low portion of each exponent are used.
摘要翻译： 公开了一种用于确定两个浮点数的两个指数之间的差异的装置和方法。 每个数字的指数分为两部分。 高部分包含最高有效位，而低部分包含最低有效位。 低部分中的比特数与每个浮点数的分数部分中的比特数有关。 为了确定需要在其中一个指数中移位的差异，基于相对于高部分之间的差异找到几个条件中的哪一个来选择指数的低部分之间的差异之一。 有利地，使用与每个指数的低部分中的位数一样宽的一组加法器。
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公开(公告)号：US20120265793A1
公开(公告)日：2012-10-18
申请号：US13085305
申请日：2011-04-12
申请人： George Q. PHAN , Scott A. HILKER
发明人： George Q. PHAN , Scott A. HILKER
CPC分类号： G06F7/607 , G06F7/4876
摘要： A merged compressor flip-flop circuit is provided. The circuit includes a compressor circuit having a front-end and a back-end, the front-end configured to receive four input bits and to output a first carry-bit to a back-end of a second compressor circuit, the front end further configured to output intermediate sum signals to the back-end of the compressor circuit, the back-end configured to receive the intermediate sum signals from the front-end and further configured to receive a second carry-bit from a front-end of a third compressor circuit, the back-end further configured to output a sum-bit and a third carry-bit based upon the intermediate sum signals and the second carry-bit, and a flip-flop circuit configure to receive the sum-bit and third carry-bit and to store the sum-bit and third carry-bit, wherein the back-end of the compressor circuit directly drives the sum-bit and third carry-bit into the flip-flop circuit
摘要翻译： 提供了一种合并的压缩器触发器电路。 电路包括具有前端和后端的压缩机电路，前端被配置为接收四个输入位并将第一进位位输出到第二压缩机电路的后端，前端进一步 被配置为将中间和信号输出到压缩机电路的后端，后端被配置为从前端接收中间和信号，并进一步被配置为从第三端的前端接收第二进位位 压缩机电路，后端还被配置为基于中间和信号和第二进位位输出和位和第三进位位，并且触发器电路配置为接收和位和第三进位 并且存储和位和第三进位位，其中压缩器电路的后端直接将和位和第三进位位驱动到触发器电路中
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公开(公告)号：US20110208951A1
公开(公告)日：2011-08-25
申请号：US12709945
申请日：2010-02-22
申请人： Scott A. Hilker
发明人： Scott A. Hilker
CPC分类号： G06F9/30036 , G06F9/30109
摘要： A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first access port of the register file to access a first portion of the instruction operand. A second portion of the execution unit provides a second access request to a second access port of the register file to access a second portion of the instruction operand. The register file can be configured into physically separate portions.
摘要翻译： 公开了执行程序指令的方法。 存储在寄存器文件的寄存器中的指令操作数由执行单元使用多个访问请求来访问。 执行单元的第一部分向寄存器文件的第一访问端口提供第一访问请求以访问指令操作数的第一部分。 执行单元的第二部分向寄存器文件的第二访问端口提供第二访问请求以访问指令操作数的第二部分。 寄存器文件可以配置成物理上分开的部分。
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公开(公告)号：US4941120A
公开(公告)日：1990-07-10
申请号：US339347
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49947
摘要： Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.
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8.发明授权
公开(公告)号：US4926370A
公开(公告)日：1990-05-15
申请号：US339348
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49957
摘要： A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.
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公开(公告)号：US20130346463A1
公开(公告)日：2013-12-26
申请号：US13529619
申请日：2012-06-21
申请人： Scott A. Hilker , George Q. Phan
发明人： Scott A. Hilker , George Q. Phan
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/483 , G06F7/4876 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F2207/382 , G06F2207/3884
摘要： The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.
摘要翻译： 所公开的实施例涉及用于准确，有效和快速地执行乘法指令的装置。 所公开的实施例可以提供具有优化布局的乘法器模块，其可以在乘法运算期间有助于加速结果的计算，从而可以减少周期延迟，从而可以降低功耗。
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10.发明授权Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor 有权使用饱和度进行乘法和乘法运算的算术处理单元及其方法公开(公告)号：US08316071B2
公开(公告)日：2012-11-20
申请号：US12472715
申请日：2009-05-27
申请人： Kevin A. Hurd , Scott A. Hilker
发明人： Kevin A. Hurd , Scott A. Hilker
CPC分类号： G06F7/4991 , G06F7/49921 , G06F7/53 , G06F7/5443
摘要： Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.
摘要翻译： 形成表示第一和第二操作数的乘积的和和进位信号。 形成具有由第一和第二操作数的乘积的符号确定的值的偏置信号。 基于和信号，进位信号，符号扩展加数和偏置信号的相加来提供输出信号。 基于产品的符号和输出信号的符号，选择输出信号的一部分，饱和最小值或饱和最大值作为最终结果。
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