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11.发明授权公开(公告)号：US06798827B1
公开(公告)日：2004-09-28
申请号：US09569828
申请日：2000-05-12
申请人： Abhijit M. Phanse
发明人： Abhijit M. Phanse
IPC分类号： H04B138
CPC分类号： H04L25/0296 , H04B3/23
摘要： A method corrects an input DC offset signal generated in front-end analog signal processing circuitry in a transceiver capable of operating in a high frequency local area network. An output signal from the front-end analog signal processing circuitry of the transceiver is received in a DC offset correction controller. A DC offset signal component in the output signal from the front-end analog signal processing circuitry due to an accrued DC offset is detected. A DC offset correction signal is sent from the DC offset correction controller to an adjustable biasing circuit coupled to a differential amplifier of a receiver line driver of the transceiver to modify the DC offset signal component.
摘要翻译： 一种方法校正在能够在高频局域网中操作的收发机中的前端模拟信号处理电路中产生的输入DC偏移信号。 在DC偏移校正控制器中接收来自收发器的前端模拟信号处理电路的输出信号。 检测来自前端模拟信号处理电路的输出信号中由于累积DC偏移引起的DC偏移信号分量。 DC偏移校正信号从DC偏移校正控制器发送到可调偏置电路，该可调偏置电路耦合到收发器的接收器线路驱动器的差分放大器，以修改DC偏移信号分量。
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公开(公告)号：US06407637B1
公开(公告)日：2002-06-18
申请号：US09569964
申请日：2000-05-12
IPC分类号： H03F345
CPC分类号： H03F3/45183 , H03F3/45632 , H03F2203/45344 , H03F2203/45571 , H03F2203/45702
摘要： There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
摘要翻译： 公开了一种差分电流镜系统和方法，用于提供差分输出电流信号，其中差分输入电流信号与共模电流信号被拒绝。 该系统包括一对二极管连接的晶体管和差分放大器。 一对二极管连接的晶体管包括耦合在一起的第一和第二晶体管。 差分放大器包括以差分放大器配置耦合在一起的第三和第四晶体管。 第三晶体管的栅极接收来自第一晶体管的漏极的第一输入电流信号，第四晶体管的栅极从第二晶体管的漏极接收第二输入电流信号。
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13.发明授权System and method for cancelling signal echoes in a full-duplex transceiver front end 有权用于在全双工收发器前端消除信号回波的系统和方法公开(公告)号：US07457386B1
公开(公告)日：2008-11-25
申请号：US11602484
申请日：2006-11-20
申请人： Abhijit M. Phanse
发明人： Abhijit M. Phanse
IPC分类号： H04B1/10
CPC分类号： H04B3/23
摘要： There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.
摘要翻译： 公开了一种用于全双工收发器的回波消除器电路，其包括能够通过电缆发送模拟发射信号的线路驱动器并且包括能够从电缆接收模拟接收信号的线路接收器的线路接收机。 回波消除器阻抗模型电路耦合到线路驱动器的输出端并耦合到线路接收机的输入。 回波消除器阻抗模型电路产生质量相等并且与表示模拟接收信号中存在的信号回波的电流相位相反的回波消除器电流。 回波消除器阻抗模型电路具有用于产生回波消除器电流的可变阻抗。 可变阻抗具有至少一个可变电阻和至少一个可变电容。 回波消除器阻抗模型电路中的电阻和电容值响应于来自回波消除器控制电路的控制信号而变化，以补偿和消除信号回波。
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公开(公告)号：US07061978B2
公开(公告)日：2006-06-13
申请号：US10244500
申请日：2002-09-16
CPC分类号： H04L25/03878
摘要： In accordance with the presently claimed invention, compensation for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
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公开(公告)号：US06590454B2
公开(公告)日：2003-07-08
申请号：US10100433
申请日：2002-03-18
IPC分类号： H03F345
CPC分类号： H03F3/345 , H03F1/301 , H03F3/45713 , H03F2200/456 , H03G1/00
摘要： There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
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公开(公告)号：US06373338B1
公开(公告)日：2002-04-16
申请号：US09569958
申请日：2000-05-12
IPC分类号： H03F345
CPC分类号： H03F3/45183 , H03F2203/45344 , H03F2203/45544
摘要： There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
摘要翻译： 公开了一种差分电流镜系统和方法，用于提供差分输出电流信号，其中差分输入电流信号与共模电流信号被拒绝。 该系统包括一对二极管连接的晶体管和差分放大器。 一对二极管连接的晶体管包括耦合在一起的第一和第二晶体管。 差分放大器包括以差分放大器配置耦合在一起的第三和第四晶体管。 第三晶体管的栅极接收来自第一晶体管的漏极的第一输入电流信号，第四晶体管的栅极从第二晶体管的漏极接收第二输入电流信号。
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公开(公告)号：US06359511B1
公开(公告)日：2002-03-19
申请号：US09570082
申请日：2000-05-12
IPC分类号： H03F345
CPC分类号： H03F3/345 , H03F1/301 , H03F3/45713 , H03F2200/456 , H03G1/00
摘要： There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
摘要翻译： 公开了用于可变增益控制的电流分配的系统和方法。 该系统包括电流分流电路，其将输入电流分成与第一比例因子成比例的第一电流部分，该第一比例因子具有在零和一之间的值。 电流的剩余部分是与具有等于1的值减去第一比例因子的第二比例因子成比例的第二电流部分。 电流分流电路包括抑制共模输入电流信号的差分电流镜电路。
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18.发明授权System and method for cancelling signal echoes in a full-duplex transceiver front end 有权用于在全双工收发器前端消除信号回波的系统和方法公开(公告)号：US07139342B1
公开(公告)日：2006-11-21
申请号：US09569957
申请日：2000-05-12
申请人： Abhijit M. Phanse
发明人： Abhijit M. Phanse
IPC分类号： H04B1/10
CPC分类号： H04B3/23
摘要： There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.
摘要翻译： 公开了一种用于全双工收发器的回波消除器电路，其包括能够通过电缆发送模拟发射信号的线路驱动器并且包括能够从电缆接收模拟接收信号的线路接收器的线路接收机。 回波消除器阻抗模型电路耦合到线路驱动器的输出端并耦合到线路接收机的输入。 回波消除器阻抗模型电路产生质量相等并且与表示模拟接收信号中存在的信号回波的电流相位相反的回波消除器电流。 回波消除器阻抗模型电路具有用于产生回波消除器电流的可变阻抗。 可变阻抗具有至少一个可变电阻器和至少一个可变电容器。 回波消除器阻抗模型电路中的电阻和电容值响应于来自回波消除器控制电路的控制信号而变化，以补偿和消除信号回波。
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公开(公告)号：US07035330B2
公开(公告)日：2006-04-25
申请号：US10768408
申请日：2004-01-30
申请人： Abhijit G. Shanbhag , Qian Yu , Abhijit M. Phanse , Jishnu Bhatacharjee , Debanjan Mukherjee , Venugopal Balasubramonian , Fabian Giroud , Edem Ibragimov
发明人： Abhijit G. Shanbhag , Qian Yu , Abhijit M. Phanse , Jishnu Bhatacharjee , Debanjan Mukherjee , Venugopal Balasubramonian , Fabian Giroud , Edem Ibragimov
CPC分类号： H04L25/0307 , H03H21/0012 , H04L2025/0349 , H04L2025/03509 , H04L2025/03611
摘要： A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
摘要翻译： 具有用于自适应信号均衡器的动态反馈控制的判决反馈均衡器。 动态控制决策反馈环路内的定时，以优化输出信号限幅器对数据信号的恢复。 动态定时由形成为反馈和前馈信号的组合的信号控制。 反馈信号是与预切片器和后切片器信号之间的差异相关的误差信号。 前馈信号通过差分和延迟输入数据信号来形成。
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公开(公告)号：US07031383B2
公开(公告)日：2006-04-18
申请号：US10117293
申请日：2002-04-05
CPC分类号： H04L25/03878
摘要： A compensation circuit for reducing intersymbol interference (ISI) products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium provides for selective application of compensation to individual, discrete data signal components. According to one embodiment, one circuit branch processes the electrical data signal to substantially remove one distinct signal component representing an ISI product of some portion of the data symbol sequence. A second circuit branch approximately duplicates an ISI product of another portion of the data symbol sequence for removal by subtraction within a signal combiner from the compensated signal provided by the first circuit branch. A third circuit branch approximately duplicates an ISI product of still another portion of the data symbol sequence also for removal by subtraction within the signal combiner from the compensated signal provided by the first circuit branch.
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