公开(公告)号：US07303648B2

公开(公告)日：2007-12-04

申请号：US10854541

申请日：2004-05-25

Applicant: Hyun-Mog Park ,  Vijayakumar Ramachandrarao

Inventor： Hyun-Mog Park ,  Vijayakumar Ramachandrarao

IPC: H01L21/3065

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  Y10S438/978

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract translation: 在一个实施方案中，与集成电路器件中的蚀刻通孔相关的系统和技术包括：提供介电材料和导电材料，去除电介质材料的第一部分以在电介质材料中形成孔，执行去除 电介质材料的第二部分以形成在导电材料上接触的通孔，并且横向膨胀通孔的底部尺寸，而不会明显增加通孔的深度。 该技术还可以包括：提供具有介电材料和导电材料的基底，没有相关联的蚀刻停止层，以高蚀刻速率去除第一部分，控制离子轰击和等离子体化学以形成通孔的倾斜底部， 并执行强烈的离子轰击等离子体蚀刻，横向扩展通孔底部。