公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363360A1

公开(公告)日：2024-10-31

申请号：US18769414

申请日：2024-07-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsing OU YANG

IPC分类号： H01L21/311 ,  H01L21/027

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/31116

摘要： This disclosure provides methods of patterning a semiconductor structure. A first resist layer is patterned to form a first opening in the first resist layer. A second resist layer under the first resist layer is patterned to extend the first opening into the second resist layer, where a top surface of an oxide in the second resist layer is higher than a bottom surface of the first opening. The oxide and the second resist layer are simultaneously etched by a first etching process, where a first etching rate of the oxide is close to a second etching rate of the second resist layer. The oxide and a silicon-containing layer under the oxide are etched by a second etching process to form a second opening below the first opening, where a third etching rate of the oxide is higher than a fourth etching rate of the silicon-containing layer.

公开(公告)号：US12125743B2

公开(公告)日：2024-10-22

申请号：US18302156

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsun Wang ,  Mei-Yun Wang ,  Kuo-Yi Chao ,  Wang-Jung Hsueh

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B10/00

CPC分类号： H01L21/76816 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H10B10/12

摘要： Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

公开(公告)号：US12125710B2

公开(公告)日：2024-10-22

申请号：US17586251

申请日：2022-01-27

申请人： Tokyo Electron Limited

发明人： Sho Kumakura ,  Yusuke Takino

IPC分类号： H01L21/311 ,  H01J37/32 ,  H01L21/3065

CPC分类号： H01L21/31144 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/31116 ,  H01J2237/334

摘要： A substrate processing method includes: (a) providing a substrate including an etching target film, a first mask formed on the etching target film, and a second mask formed on the first mask, the second mask being different in film type from the first mask and having an opening; (b) selectively etching the first mask with respect to the second mask, thereby forming an opening in the first mask such that an opening dimension of at least a portion of the first mask is larger than an opening dimension of a bottom of the second mask; and (c) etching the etching target film.

公开(公告)号：US20240347345A1

公开(公告)日：2024-10-17

申请号：US18751423

申请日：2024-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC分类号： H01L21/311 ,  C23C16/452 ,  H01L21/67 ,  H01L21/677

CPC分类号： H01L21/311 ,  C23C16/452 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/67098 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67225 ,  H01L21/67248 ,  H01L21/67748

摘要： A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.

公开(公告)号：US20240339329A1

公开(公告)日：2024-10-10

申请号：US18298094

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yao-Sheng HUANG ,  Hsiang-Pi CHANG ,  Shen-Yang LEE ,  Huang-Lin CHAO

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/31116 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66621

摘要： A method for manufacturing a semiconductor structure includes trimming a semiconductor region using a gaseous halogen-based etchant such that the trimmed semiconductor region has a first part and a second part which is formed on the first part and which has a halogen-terminated trimmed surface, and treating the halogen-terminated trimmed surface of the second part using a gaseous oxidant including hydrogen and oxygen such that the second part is oxidized to form an oxidized part, and such that the halogen-terminated trimmed surface is converted into a hydroxyl group-terminated surface of the oxidized part.

公开(公告)号：US20240332029A1

公开(公告)日：2024-10-03

申请号：US18191098

申请日：2023-03-28

申请人： Tokyo Electron Limited

发明人： Du Zhang ,  Mingmei Wang

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC分类号： H01L21/31144 ,  H01L21/02211 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116

摘要： A method of processing a substrate that includes: flowing a fluorocarbon, a metal halide, and dihydrogen (H2) into a plasma processing chamber, the plasma processing chamber configured to hold a substrate including a dielectric layer including silicon oxide as an etch target and a patterned hardmask including polycrystalline silicon (poly-Si) over the dielectric layer; while flowing the gases, generating a plasma in the plasma processing chamber; and forming a high aspect ratio feature by exposing the substrate to the plasma to etch a recess in the dielectric layer, where a metal-containing passivation layer is formed over the patterned hardmask during the exposing.

公开(公告)号：US20240321937A1

公开(公告)日：2024-09-26

申请号：US18588454

申请日：2024-02-27

申请人： MICRON TECHNOLOGY, INC.

发明人： Keisuke Otsuka

IPC分类号： H01G4/30 ,  H01L21/311

CPC分类号： H01L28/40 ,  H01L21/31116 ,  H01L21/31144

摘要： A method that includes, forming a first insulating film, first etching the first insulating film to form a first cylinder having a first diameter, forming a second insulating film on the first insulating film, second etching the second insulating film to form a second cylinder overlapping the first cylinder and having a second diameter different from the first diameter, third etching the first insulating film overlapping the second cylinder, filling the first and second cylinders with a conductive material, and removing the first and second insulating films.

公开(公告)号：US20240321641A1

公开(公告)日：2024-09-26

申请号：US18606739

申请日：2024-03-15

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Jong Mun Kim ,  Jonathan Qian ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/822 ,  H01L21/311

CPC分类号： H01L21/8221 ,  H01L21/31116

摘要： A method includes forming a planarization layer to a position below an upper transistor device region of a base structure of an electronic device and above a lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming spacer material along the base structure and the planarization layer, modifying the spacer material formed along bottom trenches of the base structure to obtain modified spacer material, and forming a spacer layer by using a wet etch process to remove the modified spacer material. Modifying the spacer material formed along the bottom trenches of the base structure to obtain the modified spacer material includes performing a dry etch process targeting the spacer material formed along the bottom trenches of the base structure.

公开(公告)号：US12100600B2

公开(公告)日：2024-09-24

申请号：US17424211

申请日：2019-12-20

申请人： Central Glass Company, Limited

发明人： Hiroyuki Oomori ,  Tatsunori Kamida ,  Shinya Ikeda

IPC分类号： H01L21/31 ,  C09K13/02 ,  C09K13/08 ,  H01L21/3065 ,  H01L21/311 ,  C07C17/093 ,  C07C17/361 ,  C07C19/08

CPC分类号： H01L21/31116 ,  C09K13/02 ,  C09K13/08 ,  H01L21/3065 ,  H01L21/31138 ,  C07C17/093 ,  C07C17/361 ,  C07C19/08

摘要： A dry etching method according to one embodiment of the present disclosure includes plasmatizing a dry etching agent and etching a silicon oxide or a silicon nitride with the plasmatized dry etching agent, wherein the dry etching agent comprises CF3I and a C2-C3 fluorine-containing linear nitrile compound, and wherein the concentration of the C2-C3 fluorine-containing linear nitrile compound relative to the CF3I is higher than or equal to 1 vol. ppm and lower than or equal to 1 vol %.