公开(公告)号：US20240061805A1

公开(公告)日：2024-02-22

申请号：US17892955

申请日：2022-08-22

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Millind MITTAL

IPC: G06F15/78

CPC classification number: G06F15/7896

Abstract: Embodiments herein describe a processor system that includes an integrated, adaptive accelerator. In one embodiment, the processor system includes multiple core complex chiplets that each contain one or processing cores for a host CPU. In addition the processor system includes an accelerator chiplet. The processor system can assign one or more of the core complex chiplets to the accelerator chiplet to form an IO device while the remaining core complex chiplets form the CPU for the host. In this manner, rather than the accelerator and the CPU having independent computer resources, the accelerator can be integrated into the processor system of the host so that hardware resources can be divided between the CPU and the accelerator depending on the needs of the particular application(s) executed by the host.

公开(公告)号：US20230004442A1

公开(公告)日：2023-01-05

申请号：US17903084

申请日：2022-09-06

Applicant: XILINX, INC.

Inventor： Millind MITTAL ,  Jaideep DASTIDAR

IPC: G06F9/50 ,  G06F12/0815 ,  G06F9/38 ,  G06F9/455

Abstract: The embodiments herein describe a virtualization framework for cache coherent accelerators where the framework incorporates a layered approach for accelerators in their interactions between a cache coherent protocol layer and the functions performed by the accelerator. In one embodiment, the virtualization framework includes a first layer containing the different instances of accelerator functions (AFs), a second layer containing accelerator function engines (AFE) in each of the AFs, and a third layer containing accelerator function threads (AFTs) in each of the AFEs. Partitioning the hardware circuitry using multiple layers in the virtualization framework allows the accelerator to be quickly re-provisioned in response to requests made by guest operation systems or virtual machines executing in a host. Further, using the layers to partition the hardware permits the host to re-provision sub-portions of the accelerator while the remaining portions of the accelerator continue to operate as normal.

公开(公告)号：US20220292024A1

公开(公告)日：2022-09-15

申请号：US17826074

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： Millind MITTAL ,  Jaideep DASTIDAR

IPC: G06F12/0891 ,  G06F3/06 ,  G06F9/50 ,  G06F12/0815

Abstract: The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus, fine-grained allocation provides a flexible allocation of entries in a hardware cache that permits an administrator to reserve any number of entries for a particular tenant, but also permit other tenants to use this bandwidth when the reserved entries are not currently needed by the tenant.