公开(公告)号：US20050098795A1

公开(公告)日：2005-05-12

申请号：US10956063

申请日：2004-10-04

申请人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

发明人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L31/062

CPC分类号： H01L27/0262

摘要： A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

摘要翻译： 高压设备。 在ESD保护器件中将高电压MOS晶体管施加到其中添加掺杂区域的结构，产生具有更短放电路径的寄生半导体可控整流器（SCR），使得SCR具有更快的响应增强ESD保护。

公开(公告)号：US20100208398A1

公开(公告)日：2010-08-19

申请号：US12371092

申请日：2009-02-13

申请人： Yeh-Ning Jou

发明人： Yeh-Ning Jou

IPC分类号： H02H9/04

摘要： An ESD protection circuit coupled between a first power line and a second power line to avoid damage to an integrated circuit by an ESD event is disclosed. The ESD protection circuit includes a detection unit, a trigger unit, and a discharging unit. The detection unit asserts a detection signal when the ESD event occurs. The trigger unit asserts a first trigger signal and a second trigger signal when the detection is asserted. The discharging unit provides a discharge path to release an ESD current caused by the ESD event when the first and the second trigger signals are asserted.

摘要翻译： 公开了一种ESD保护电路，其耦合在第一电力线和第二电力线之间，以避免ESD事件对集成电路的损坏。 ESD保护电路包括检测单元，触发单元和放电单元。 当ESD事件发生时，检测单元断言检测信号。 当检测被确认时，触发单元断言第一触发信号和第二触发信号。 当第一和第二触发信号被断言时，放电单元提供放电路径以释放由ESD事件引起的ESD电流。

公开(公告)号：US20090135532A1

公开(公告)日：2009-05-28

申请号：US11946011

申请日：2007-11-27

申请人： Yeh-Ning Jou ,  Geeng-Lih Lin

发明人： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

摘要翻译： 提供静电放电（ESD）保护电路。 晶体管耦合在节点和地之间，并且具有耦合到地的栅极。 二极管链耦合在节点和焊盘之间，并且包括串联连接的多个第一二极管，其中第一二极管以正向传导方向从焊盘耦合到节点。 第二二极管耦合在节点和焊盘之间，并且第二二极管以从节点到焊盘的正向传导方向耦合。

公开(公告)号：US08643111B1

公开(公告)日：2014-02-04

申请号：US13591861

申请日：2012-08-22

申请人： Yeh-Ning Jou

发明人： Yeh-Ning Jou

IPC分类号： H01L29/93

CPC分类号： H01L27/0248 ,  H01L27/0259

摘要： An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one.

摘要翻译： 提供静电放电（ESD）保护装置。 ESD保护器件包括设置在半导体衬底上的外延层。 隔离图案设置在外延层上以限定由第一阱区域包围的第一有源区和第二有源区。 一个门设置在隔离图案上。 第一掺杂区域和第二掺杂区域分别设置在第一有源区域和第二有源区域中。 漏极掺杂区域设置在第一掺杂区域中。 源掺杂区域和第一拾取掺杂区域设置在第二掺杂区域中。 具有延伸部分的源极接触插头连接到源极掺杂区域。 覆盖第一拾取掺杂区域的延伸部分的面积与第一拾取掺杂区域的面积的比率在零和一之间。

公开(公告)号：US20120001225A1

公开(公告)日：2012-01-05

申请号：US13232975

申请日：2011-09-14

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US09236459B2

公开(公告)日：2016-01-12

申请号：US13232975

申请日：2011-09-14

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L27/02

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US07755143B2

公开(公告)日：2010-07-13

申请号：US12177773

申请日：2008-07-22

申请人： Yeh-Ning Jou ,  Geeng-Lih Lin

发明人： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC分类号： H01L23/62

CPC分类号： H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.

摘要翻译： 描述半导体器件。 该半导体器件包括在衬底的受保护器件区域中的受保护器件。 包括外部第一保护环和内部第二保护环的静电放电电力钳装置位于衬底的保护环区域中，包围受保护的器件。 第一保护环包括具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区域和具有第二导电类型的第二掺杂区域位于第一阱区域中。 第二保护环包括具有第二导电类型的第二阱区。 第三掺杂区域在第二阱区域中具有第二导电类型。 输入/输出装置在外围装置区域中，耦合到静电放电电力钳装置。

公开(公告)号：US08049307B2

公开(公告)日：2011-11-01

申请号：US12358943

申请日：2009-01-23

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/93

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US20100187566A1

公开(公告)日：2010-07-29

申请号：US12358943

申请日：2009-01-23

申请人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

发明人： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L27/0259

摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

摘要翻译： 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US07599160B2

公开(公告)日：2009-10-06

申请号：US11946011

申请日：2007-11-27

申请人： Yeh-Ning Jou ,  Geeng-Lih Lin

发明人： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC分类号： H02H9/00 ,  H02H1/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

摘要翻译： 提供静电放电（ESD）保护电路。 晶体管耦合在节点和地之间，并且具有耦合到地的栅极。 二极管链耦合在节点和焊盘之间，并且包括串联连接的多个第一二极管，其中第一二极管以正向传导方向从焊盘耦合到节点。 第二二极管耦合在节点和焊盘之间，并且第二二极管以从节点到焊盘的正向传导方向耦合。