摘要:
A variable degeneration impedance supply circuit, including: two alternatively connected transistors; a capacitor circuit having a predetermined capacitance and serially connecting output terminals of the two transistors; and a switch for controlling on/off state between the capacitor circuit and the output terminal, according to a predetermined first control signal. The circuit further includes: at least one sub capacitor circuit arrayed in parallel to the capacitor circuit for serially connecting the output terminals of the two transistors; and at least one sub switch for controlling on/off state between the sub capacitor circuit and the output terminal, according to a predetermined control signal. Therefore, the magnitude of a degeneration impedance can be varied by controlling degeneration capacitance. Moreover, the variable degeneration impedance supply circuit can be advantageously applied to a voltage controlled oscillation circuit and a frequency divider circuit.
摘要:
A variable degeneration impedance supply circuit, including: two alternatively connected transistors; a capacitor circuit having a predetermined capacitance and serially connecting output terminals of the two transistors; and a switch for controlling on/off state between the capacitor circuit and the output terminal, according to a predetermined first control signal. The circuit further includes: at least one sub capacitor circuit arrayed in parallel to the capacitor circuit for serially connecting the output terminals of the two transistors; and at least one sub switch for controlling on/off state between the sub capacitor circuit and the output terminal, according to a predetermined control signal. Therefore, the magnitude of a degeneration impedance can be varied by controlling degeneration capacitance. Moreover, the variable degeneration impedance supply circuit can be advantageously applied to a voltage controlled oscillation circuit and a frequency divider circuit.
摘要:
A transmitter having a vertical BJT, capable of reducing power consumption, carrier leakage of a local oscillator and an error vector magnitude (EVM), is disclosed. In the transmitter, vertical BJTs implemented by a standard triplex well CMOS process are used in a frequency up-mixer and a baseband analog circuit including a DAC, an LPF, a VGA and a PGA, thereby improving the overall performance of the transmitter.
摘要:
A receiver having a low computation complexity so as to estimate a transmitted includes a likelihood function calculator calculating likelihoods of transmittable signals using a currently received signal, at least one previously received signal, and an estimated signal corresponding to the at least one previously received signal; and a maximum value output unit outputting a transmittable signal corresponding to a likelihood function of the likelihood functions having a maximum value. Thus, a currently received signal can be estimated using a previously received signal, a previously estimated signal, and the currently received signal. As a result, the reliability of the estimated signal can be improved. Also, the previously estimated signal can be stored to prevent the complexity of a computation from being increased.