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231.发明授权公开(公告)号：US10999004B2
公开(公告)日：2021-05-04
申请号：US16529502
申请日：2019-08-01
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
IPC: H04L1/00 , H03M13/11 , H03M13/03 , H03M13/31 , H03M13/00 , H03M13/25 , H03M13/27 , H03M13/29 , H04L27/26
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US10979079B2
公开(公告)日：2021-04-13
申请号：US16527485
申请日：2019-07-31
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US10972131B2
公开(公告)日：2021-04-06
申请号：US16530723
申请日：2019-08-02
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US10944433B2
公开(公告)日：2021-03-09
申请号：US16528939
申请日：2019-08-01
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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235.发明授权公开(公告)号：US10931798B2
公开(公告)日：2021-02-23
申请号：US16593809
申请日：2019-10-04
Inventor： Jae-Young Lee , Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Heung-Mook Kim
Abstract: An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing time interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).
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Patent Agency Ranking
公开(公告)号：US10903856B2
公开(公告)日：2021-01-26
申请号：US16540991
申请日：2019-08-14
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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237.发明授权公开(公告)号：US10892924B2
公开(公告)日：2021-01-12
申请号：US16797845
申请日：2020-02-21
Inventor： Jae-Hwui Bae , Sun-Hyoung Kwon , Young-Su Kim , Dong-Joon Choi , Nam-Ho Hur
Abstract: Disclosed herein is a demodulation method of a Layer-Division Multiplexing (LDM) system. The demodulation method may include receiving an LDM modulation signal, restoring a first-layer signal from the LDM modulation signal and remodulating the first-layer signal, restoring and remodulating a second-layer signal by performing cancellation of the amplitude component of the first-layer signal from the LDM modulation signal using signaling information independently of restoration and remodulation of the first-layer signal, and restoring a third-layer signal using the first-layer signal, the second-layer signal, and the LDM modulation signal.
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238.发明授权公开(公告)号：US10797830B2
公开(公告)日：2020-10-06
申请号：US16791822
申请日：2020-02-14
Inventor： Nam-Ho Hur , Sun-Hyoung Kwon , Sung-Ik Park , Heung-Mook Kim , Jae-Young Lee
Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
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公开(公告)号：US10797822B2
公开(公告)日：2020-10-06
申请号：US16401006
申请日：2019-05-01
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
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公开(公告)号：US10778817B2
公开(公告)日：2020-09-15
申请号：US16313790
申请日：2017-07-05
Inventor： Bo-Mi Lim , Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.
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