公开(公告)号：US07379352B1

公开(公告)日：2008-05-27

申请号：US11104077

申请日：2005-04-11

Applicant: David V. James ,  Jagadeesan Rajamanickam

Inventor： David V. James ,  Jagadeesan Rajamanickam

IPC: G11C7/06

CPC classification number: G11C15/00

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract translation: 公开了一种搜索引擎系统（100），其可以包括以级联配置布置的至少一个内容可寻址存储器（CAM）设备（102），其至少一个存储器设备（104），诸如静态随机存取存储器（SRAM） 。 CAM设备（102）和存储设备（104）可以通过点对点单向连接彼此连接。 由诸如网络处理单元（NPU）（110）的设备发布的命令数据可以流过从CAM设备（102）开始的所有设备，并且最终到达存储设备（104）。 存储器装置（104）可以将其自己的当前结果数据与流（例如另一RAM装置）中的先前装置的数据进行比较，并产生输出响应。

公开(公告)号：US20080071757A1

公开(公告)日：2008-03-20

申请号：US11524024

申请日：2006-09-19

Applicant: Michael E. Ichiriu ,  Martin Fabry ,  Larry A. Wall ,  Ajit V. Ninan

Inventor： Michael E. Ichiriu ,  Martin Fabry ,  Larry A. Wall ,  Ajit V. Ninan

IPC: G06F17/30

CPC classification number: G06F17/30864 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99936

Abstract: A search engine configured to determine whether an input string including a plurality of input characters matches a regular expression including an inexact pattern including a specified range of instances of pattern characters each belonging to a specified set of characters, the search engine including a microcontroller having an input to receive a microprogram embodying the inexact pattern, a first co-processor coupled to the microcontroller and dedicated to determine whether each input character in a first portion of the input string is a member of the specified set of characters, and a second co-processor coupled to the microcontroller and dedicated to determine whether the number of input characters in the first portion of the input string falls within the specified range.

Abstract translation: 一种搜索引擎，被配置为确定包括多个输入字符的输入字符串是否包括包括不同于特定模式的正则表达式的正则表达式，所述不精确模式包括每个属于指定字符集的模式字符的实例的指定范围，所述搜索引擎包括具有 输入以接收体现不精确模式的微程序，第一协处理器耦合到微控制器并专用于确定输入串的第一部分中的每个输入字符是否是指定字符集的成员， 处理器耦合到微控制器并专用于确定输入串的第一部分中的输入字符的数量是否在规定的范围内。

公开(公告)号：US07339810B1

公开(公告)日：2008-03-04

申请号：US11089837

申请日：2005-03-24

Applicant: Scott Smith

Inventor： Scott Smith

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A search engine system (100) can include a key multiplexer (104) and logic circuit (108). A key from a previous operation can be received by logic circuit (108) and altered to generate an idle key. In a non-search operation, the idle key can be applied to a CAM section to draw current as in a normal search operation. Logic circuit (108) can ensure that an idle key value is always different than a previously applied key value.

Abstract translation: 搜索引擎系统（100）可以包括密钥多路复用器（104）和逻辑电路（108）。 来自先前操作的键可由逻辑电路（108）接收并改变以产生空闲键。 在非搜索操作中，空闲键可以应用于CAM部分以在正常搜索操作中绘制电流。 逻辑电路（108）可以确保空闲键值总是与先前应用的键值不同。

公开(公告)号：US07325091B2

公开(公告)日：2008-01-29

申请号：US10855580

申请日：2004-05-26

Applicant: Jose Pio Pereira

Inventor： Jose Pio Pereira

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A CAM device having a plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding block select circuit and to an address translation circuit. Each block select circuit provides a select signal to a corresponding CAM block to selectively enable or disable the CAM block. The address translation circuit includes logic that translates address space from disabled (e.g., defective) CAM blocks to enabled (e.g., non-defective) CAM blocks. During read and write operations, an address to access a row in a first of the CAM blocks is received into the address translation logic. If the first CAM block is disabled, the address translation logic translates the address to access a row in a second of the CAM blocks. Conversely, if the first CAM block is enabled, the address translation logic facilitates access to the row in the first CAM block.

Abstract translation: 具有多个CAM块的CAM设备包括用于禁用一个或多个有缺陷的CAM块的电路，并且将禁用的CAM块中的地址空间选择性地转换为剩余的启用的CAM块。 在一个实施例中，每个CAM块耦合到对应的块选择电路和地址转换电路。 每个块选择电路向对应的CAM块提供选择信号以选择性地启用或禁用CAM块。 地址转换电路包括将地址空间从禁用（例如，有缺陷的）CAM块转换为启用（例如，无缺陷）的CAM块的逻辑。 在读取和写入操作期间，访问第一个CAM块中的行的地址被接收到地址转换逻辑中。 如果第一个CAM块被禁用，则地址转换逻辑将地址转换为访问第二个CAM块中的一行。 相反，如果第一CAM块被使能，则地址转换逻辑便于访问第一CAM块中的行。

公开(公告)号：US07317628B1

公开(公告)日：2008-01-08

申请号：US11257255

申请日：2005-10-24

Applicant: Anita X. Meng

Inventor： Anita X. Meng

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/067

Abstract: A sense amplifier circuit with faster sensing speed and improved insensitivities to fabrication process variations (i.e., eliminated functional failures) is provided herein. According to one embodiment, the sense amplifier circuit associated with a row of memory cells within a memory device may include a charging portion, which is coupled for receiving a reference voltage that is supplied to at least one additional sense amplifier circuit within the memory device. The reference voltage is provided by a current reference generator, which is coupled to the sense amplifier circuit(s) for detecting: (i) a maximum amount of current that can pass through one compare stack within the memory cell array, or (ii) a difference between the maximum amount of current and the current contribution of an n-channel current source within the sense amplifier circuit. A memory device and method of operating one embodiment of the improved sense amplifier circuit are also provided herein.

Abstract translation: 本文提供了具有更快的感测速度和对制造工艺变化（即，消除的功能故障）的不敏感性的读出放大器电路。 根据一个实施例，与存储器装置内的一行存储器单元相关联的读出放大器电路可以包括充电部分，其被耦合用于接收提供给存储器件内的至少一个附加读出放大器电路的参考电压。 参考电压由电流参考发生器提供，电流参考发生器耦合到读出放大器电路，用于检测：（i）可以通过存储器单元阵列内的一个比较堆栈的最大电流量，或者（ii） 在感测放大器电路内的最大电流和n沟道电流源的电流贡献之间的差。 还提供了一种操作改进的读出放大器电路的一个实施例的存储器件和方法。

公开(公告)号：US07307861B1

公开(公告)日：2007-12-11

申请号：US11647696

申请日：2006-12-28

Applicant: Roger Bettman ,  Eric H. Voelkel

Inventor： Roger Bettman ,  Eric H. Voelkel

IPC: G11C15/00 ,  G11C11/00 ,  G11C7/10 ,  G11C7/06 ,  G06F12/00

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract translation: 三元内容可寻址存储器（TCAM）单元（100）可以包括具有每个存储器元件的单个位线（106-0和106-1）的两个存储器元件（102-0和102-1）。 TCAM单元（100）还可以包括可连接到每个存储器元件（102-0和102-1）的比较堆栈（104）和两个字线（114和116）。 存储器元件（102-0和102-1）可以包括SRAM型存储器单元，其中两个数据端子中的一个连接到预写电位（Vpre，其可以是地电位等）。 在通过位线（106-0和106-1）提供写数据之前，写操作可以包括将存储元件（102-0和102-1）的数据值预先设置为预写电位。

公开(公告)号：US07304873B1

公开(公告)日：2007-12-04

申请号：US11043391

申请日：2005-01-25

Applicant: Pankaj Gupta

Inventor： Pankaj Gupta

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G06F11/1068 ,  G11C2029/0409 ,  G11C2207/104

Abstract: A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value that includes a key portion (KEY) and replicated key portion (KEY(REP)).

Abstract translation: CAM系统（200）可以包括具有用于存储数据值（例如，E 1）的一部分和用于存储复制数据值（E 1（REP））的另一部分的多个条目（202-0至202-3） ）。 对于即时纠错，可以通过应用包括密钥部分（KEY）和复制密钥部分（KEY（REP））的附加密钥值来搜索条目。

公开(公告)号：US07298635B1

公开(公告)日：2007-11-20

申请号：US11376764

申请日：2006-03-15

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) cell circuit can include a match section that enables an impedance path coupled to a match line in response to a comparison between a data value and a compare data value. At least a first storage circuit can be connected to the match section, and provides the data value on a first storage node and a complementary data value on a second storage node. At least a first bit line can be coupled to the first storage node by a first access controllable impedance path and coupled to the second storage node by a second access controllable impedance path.

Abstract translation: 内容可寻址存储器（CAM）单元电路可以包括匹配部分，其响应于数据值和比较数据值之间的比较，使得能够耦合到匹配线的阻抗路径。 至少第一存储电路可以连接到匹配部分，并且在第一存储节点上提供数据值和在第二存储节点上提供互补数据值。 至少第一位线可以通过第一访问可控阻抗路径耦合到第一存储节点，并且通过第二访问可控阻抗路径耦合到第二存储节点。

公开(公告)号：US07254748B1

公开(公告)日：2007-08-07

申请号：US10685026

申请日：2003-10-14

Applicant: Andrew J. Wright ,  Eric H. Voelkel ,  Srinivasan Venkatachary ,  Rochan Sankar

Inventor： Andrew J. Wright ,  Eric H. Voelkel ,  Srinivasan Venkatachary ,  Rochan Sankar

IPC: G06F11/00

CPC classification number: G06F11/1064

Abstract: A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entries producing those false matches. While the entries producing a match should have the same index location, errors might cause those match lines to have an offset. If so, the present CAM, through use of duplicative sets of CAM locations, will detect the offset and thereafter the values in each index location that produces a match, along with the corresponding parity or error detection encoding bit(s). If the parity or error detection encoding bit(s) indicate an error in a particular entry, then that error is located and the corresponding entry at the same index within the other, duplicative set of CAM locations is copied into the that erroneous entry. Since duplicative copies are by design placed into the first and second sets of CAM locations, whatever value exists in the opposing entry can be written into the erroneous entry to correct errors in that search location. The first and second sets of CAM locations are configurable to be duplicative or distinct in content, allowing error detection and correction to be performed at multiple user-specified granularities. The error detection and correction during search is backward compatible to interim parity scrubbing and ECC scan, as well as use of FNH bits set by a user or provider.

Abstract translation: 提出了CAM和CAM的操作方法。 CAM数据库的副本被复制并放置在第一组CAM位置和第二组CAM位置中。 误差检测器用于在产生这些假匹配的条目中的软错误的情况下确定错误匹配。 虽然产生匹配的条目应该具有相同的索引位置，但是错误可能导致这些匹配行具有偏移量。 如果是这样，通过使用CAM位置的重复集合，当前的CAM将检测偏移，然后检测产生匹配的每个索引位置中的值以及相应的奇偶校验或错误检测编码位。 如果奇偶校验或错误检测编码位指示特定条目中的错误，则该错误被定位，并且另一个重复的CAM位置集合中相同索引处的相应条目被复制到该错误条目中。 由于通过设计将重复副本放置在第一和第二组CAM位置中，所以相反条目中存在的任何值都可以被写入错误的条目中以纠正该搜索位置中的错误。 第一和第二组CAM位置可配置为内容重复或不同，允许以多个用户指定的粒度执行错误检测和校正。 搜索期间的错误检测和校正向后兼容到临时奇偶校验和ECC扫描，以及使用由用户或提供者设置的FNH位。

公开(公告)号：US07251707B1

公开(公告)日：2007-07-31

申请号：US10774168

申请日：2004-02-06

Applicant: Jose P Pereira

Inventor： Jose P Pereira

IPC: G06F12/00

CPC classification number: G11C15/00 ,  Y10S707/99936

Abstract: A content addressable memory includes a plurality of CAM blocks, each including an array of CAM cells to store a predetermined range of data values, a parsing circuit having an input to receive the search key and having an output to provide a selected portion of the search key in response to a select signal, and a plurality of block select circuits, each configured to enable a corresponding CAM block if the selected portion of the search key falls within the predetermined range of data values for the corresponding CAM block.

Abstract translation: 内容可寻址存储器包括多个CAM块，每个CAM块包括用于存储预定范围的数据值的CAM单元阵列;解析电路，具有用于接收搜索关键字并具有输出以提供搜索的所选部分的输入 响应于选择信号的键和多个块选择电路，每个块选择电路被配置为如果搜索关键字的所选部分落入相应CAM块的数据值的预定范围内，则启用相应的CAM块。