公开(公告)号：US12112824B2

公开(公告)日：2024-10-08

申请号：US18149675

申请日：2023-01-04

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Guifen Yang ,  Sungsoo Chi

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC分类号： G11C7/067 ,  G11C7/1096 ,  G11C7/12

摘要： Embodiments relate to a sense amplifier circuit and a data read method. The sense amplifier circuit includes: a first P-type transistor connected to a first signal terminal; a second P-type transistor connected to a second signal terminal; a first N-type transistor connected to a third signal terminal; a second N-type transistor connected to a fourth signal terminal; a first offset cancellation subcircuit configured to connect a first read bit line to a second complementary read bit line in response to a first offset cancellation signal; a second offset cancellation subcircuit configured to connect a first complementary read bit line to a second read bit line in response to a second offset cancellation signal; a first write-back subcircuit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal; and a second write-back subcircuit.

公开(公告)号：US20240170031A1

公开(公告)日：2024-05-23

申请号：US18424164

申请日：2024-01-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC分类号： G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

CPC分类号： G11C7/08 ,  G11C7/067 ,  G11C7/1039 ,  G11C11/1673 ,  G11C29/42

摘要： A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US20240127877A1

公开(公告)日：2024-04-18

申请号：US18047568

申请日：2022-10-18

申请人： Micron Technology, Inc.

发明人： Durai Vishak Nirmal Ramaswamy ,  Giorgio Servalli ,  Angelo Visconti ,  Marcello Mariani ,  Alessandro Calderoni

IPC分类号： G11C11/22 ,  G11C7/06

CPC分类号： G11C11/2257 ,  G11C7/067 ,  G11C11/2297

摘要： Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

公开(公告)号：US20240127868A1

公开(公告)日：2024-04-18

申请号：US18046961

申请日：2022-10-17

申请人： GlobalFoundries U.S. Inc.

发明人： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC分类号： G11C7/067 ,  G11C7/109 ,  G11C7/12

摘要： Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US20240105239A1

公开(公告)日：2024-03-28

申请号：US17953094

申请日：2022-09-26

申请人： MACRONIX International Co., Ltd.

发明人： Jung-Chuan Ting ,  I-Chen Yang

IPC分类号： G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC分类号： G11C7/1057 ,  G11C7/067 ,  G11C7/12

摘要： A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

公开(公告)号：US20240005966A1

公开(公告)日：2024-01-04

申请号：US17936107

申请日：2022-09-28

申请人： Changxin Memory Technologies, Inc.

发明人： FENG LIN

IPC分类号： G11C7/06 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C7/067 ,  G11C7/222 ,  G11C7/1063

摘要： Embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a memory device. The data receiving circuit includes: a first amplification module configured to: receive a data signal, a first reference signal, and a second reference signal; and when an enable signal is at a first level, in response to a sampling clock signal and on the basis of a feedback signal, select the data signal and the first reference signal for first comparison and output a first signal pair, or select the data signal and the second reference signal for second comparison and output a second signal pair; and a second amplification module configured to receive output signals of the first amplification module as an input signal pair, perform amplification processing on a voltage difference of the input signal pair.

公开(公告)号：US20240005965A1

公开(公告)日：2024-01-04

申请号：US17934695

申请日：2022-09-23

申请人： Changxin Memory Technologies, Inc.

发明人： FENG LIN

IPC分类号： G11C7/06 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C7/067 ,  G11C7/222 ,  G11C7/1063

摘要： Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.

公开(公告)号：US20230410853A1

公开(公告)日：2023-12-21

申请号：US18178135

申请日：2023-03-03

申请人： Kioxia Corporation

发明人： Akira KATAYAMA ,  Kosuke HATSUDA

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C5/06

CPC分类号： G11C7/067 ,  G11C7/1069 ,  G11C5/063

摘要： A memory system according to an embodiment includes a plurality of first wirings, a plurality of second wirings, a memory cell, a third wiring, a sense amplifier, a first switching element, a first transistor including a first terminal connected to a first node and a second terminal connected to a second node, and a control circuit. The first node is positioned further to the side of the sense amplifier than the first switching element. The second node is positioned further to the memory cell than the first switching element. The control circuit is configured to connect the first node and the second node when the first switching element is in an ON state, and connect the first node and the gate terminal of the first transistor when the first switching element is in an OFF state.

公开(公告)号：US20190096498A1

公开(公告)日：2019-03-28

申请号：US16203340

申请日：2018-11-28

申请人： MagnaChip Semiconductor, Ltd.

发明人： Duk Ju JEONG

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  G11C7/067 ,  G11C7/106 ,  G11C16/24 ,  G11C16/26 ,  G11C17/16

摘要： A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier. The sense amplifier is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line. The sense amplifier includes a precharge device that is turned on or turned off based on a read control signal, and a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.

公开(公告)号：US20190096465A1

公开(公告)日：2019-03-28

申请号：US16184719

申请日：2018-11-08

申请人： Micron Technology, Inc.

发明人： Giulio Giuseppe Marotta ,  Marco Domenico Tiburzi

IPC分类号： G11C11/22 ,  G11C11/56

CPC分类号： G11C11/2273 ,  G11C7/062 ,  G11C7/067 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/5657 ,  G11C2213/77

摘要： Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.