公开(公告)号：US11342214B1

公开(公告)日：2022-05-24

申请号：US17692146

申请日：2022-03-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.

公开(公告)号：US11327227B2

公开(公告)日：2022-05-10

申请号：US17492627

申请日：2021-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12 ,  H01L25/16

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US11315965B2

公开(公告)日：2022-04-26

申请号：US17487369

申请日：2021-09-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/146 ,  H01L33/16 ,  H01L25/075 ,  H01L27/15 ,  H01L33/62

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs); a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm; and further including a third single crystal layer including at least one LED driving circuit.

公开(公告)号：US20220026636A1

公开(公告)日：2022-01-27

申请号：US17492627

申请日：2021-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12 ,  H01L25/16

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20210296155A1

公开(公告)日：2021-09-23

申请号：US17340477

申请日：2021-06-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer, first transistors and a first metal layer; memory control circuits comprising said first transistors; a second level disposed above said first level, said second level comprising second transistors; a third level disposed above said second level, said third level comprising a plurality of third transistors; wherein said third transistors are aligned to said first transistors with a less than 40 nm alignment error, wherein said second level comprises a plurality of first memory cells, wherein said third level comprises a plurality of second memory cells, wherein one of said second transistors is at least partially self-aligned to at least one of said third transistors, being processed following a same lithography step, wherein at least one of said second memory cells comprises at least one of said third transistors, wherein said memory cells comprise a NAND non-volatile memory type.

公开(公告)号：US20210265410A1

公开(公告)日：2021-08-26

申请号：US17317894

申请日：2021-05-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L23/544

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors and alignment marks; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the third level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.

公开(公告)号：US20210257244A1

公开(公告)日：2021-08-19

申请号：US17232129

申请日：2021-04-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second level including a second single crystal layer, the second level including second transistors; and a third level including a third single crystal layer, the third level including third transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, where the second level includes a first array of first memory cells, and where the third level includes a second array of second memory cells.

公开(公告)号：US20210249473A1

公开(公告)日：2021-08-12

申请号：US17223822

申请日：2021-04-06

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H01L27/22

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and include a gate dielectric, where the gate dielectric includes hafnium oxide, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20210249296A1

公开(公告)日：2021-08-12

申请号：US17232122

申请日：2021-04-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).

公开(公告)号：US20210242368A1

公开(公告)日：2021-08-05

申请号：US17216597

申请日：2021-03-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L33/16 ,  H01L33/62 ,  H01L27/15 ,  H01L25/075

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs), a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.