-
公开(公告)号：US20210256889A1
公开(公告)日：2021-08-19
申请号：US17262775
申请日：2020-06-02
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a plurality of clock signal lines and a plurality of testing terminals. As at least two of the plurality of clock signal lines may be connected to a same testing terminal, as compared with the arrangement of the related art in which one clock signal line is connected to one testing terminal, the array substrates provided by the embodiments of the present disclosure only need to have less testing terminals, and correspondingly, the testing device that is connected to the testing terminals of the array substrate provided by the embodiments of the present disclosure may contain less pins. Therefore, the testing device can have a relatively low production cost and a relatively small volume.
-
公开(公告)号：US20210233982A1
公开(公告)日：2021-07-29
申请号：US16638556
申请日：2019-09-04
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
Abstract: An array substrate includes a base substrate (1); a driving transistor (2) on the base substrate (1); an insulating layer (3) on the driving transistor (2), the insulating layer (3) comprising a via hole above a first electrode (21) of the driving transistor (2); a conductive portion (4) on the insulating layer (3); and a light emitting device (6) on the conductive portion (4) and electrically connected to the conductive portion (4). The conductive portion (4) may be electrically connected to the first electrode (21) of the driving transistor (2) through the via hole. The light emitting device (6) may be above the via hole, and an orthographic projection of the light emitting device (6) on the base substrate (1) may cover an orthographic projection of the via hole on the base substrate (1).
-
公开(公告)号：US11074868B2
公开(公告)日：2021-07-27
申请号：US16823680
申请日：2020-03-19
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Song Meng
IPC: G09G3/325 , G09G3/3291 , G09G3/3266
Abstract: Embodiments of the present disclosure provide a pixel circuit, a display panel, and a display device. The pixel circuit includes: a first transistor; a light emitting unit, a cathode being grounded; a second transistor; a third transistor; a fourth transistor; and a capacitor, a first terminal being coupled to the control electrode of the third transistor, and a second terminal being coupled to the second electrode of the third transistor.
-
公开(公告)号：US20210226150A1
公开(公告)日：2021-07-22
申请号：US17256085
申请日：2020-04-17
Inventor： Wenbin Jia , Xinwei Gao , Peng Li
Abstract: A packaging structure, a packaging method, and a display apparatus are disclosed. The packaging structure includes: a first substrate and a second substrate opposite to each other; a plurality of first sealing frames located between the first substrate and the second substrate, wherein the first substrate, the second substrate and the plurality of first sealing frames enclose a plurality of sealed cavities not communicating with each other, and each of the sealed cavities is configured to package at least one to-be-packaged unit of a to-be-packaged device; and a first filler located in the sealed cavity.
-
公开(公告)号：US20210202604A1
公开(公告)日：2021-07-01
申请号：US16977510
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Dacheng ZHANG , Lang LIU
IPC: H01L27/32
Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.
-
Patent Agency Ranking
公开(公告)号：US20210201807A1
公开(公告)日：2021-07-01
申请号：US16766450
申请日：2019-11-04
Inventor： Xuehuan FENG , Yongqian LI , Can YUAN , Meng LI , Zehua DING , Zhidong YUAN
IPC: G09G3/3266 , G09G3/3225 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-unit and a leakage prevention circuit; the first sub-unit includes a first input circuit and a first output circuit. The first input circuit controls a level of a first node in response to a first input signal, the first output circuit provides an output signal at an output terminal under control of the level of the first node, the leakage prevention circuit is connected to the first node and a first voltage terminal, and controls a level of a leakage prevention node under control of the level of the first node, whereby a conductive path is formed between the leakage prevention node and the first voltage terminal, and a circuit connected between the first node and the leakage prevention node is turned off.
-
公开(公告)号：US20210166603A1
公开(公告)日：2021-06-03
申请号：US17052135
申请日：2019-08-08
Inventor： Xuehuan FENG , Yongqian LI
Abstract: A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.
-
278.发明申请公开(公告)号：US20210150988A1
公开(公告)日：2021-05-20
申请号：US16642469
申请日：2019-07-29
Inventor： Zhidong YUAN , Yongqian LI , Meng LI , Can YUAN
IPC: G09G3/3266 , G11C19/28
Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.
-
公开(公告)号：US20210125568A1
公开(公告)日：2021-04-29
申请号：US17081384
申请日：2020-10-27
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
IPC: G09G3/3291
Abstract: The present disclosure provides a display panel, a method thereof and a display device. The display panel includes a gate line group, a gate driving circuit, and a sub-pixel unit group. The sub-pixel unit group includes N rows of sub-pixel units, the gate line group includes (N+1) gate lines. The sub-pixel unit includes a light emitting unit, a pixel driving circuit, and a sensing circuit. The gate driving circuit includes output terminals, and is configured to sequentially output gate scanning signals through the output terminals. Each gate line is coupled to one corresponding output terminal. In the sub-pixel unit group, the pixel driving circuit in a sub-pixel unit in an n-th row is coupled to an n-th gate line; and the sensing circuit in the sub-pixel unit in the n-th row is coupled to a (n+1)-th gate line, where 1≤n≤N, and n is an integer.
-
公开(公告)号：US20210074210A1
公开(公告)日：2021-03-11
申请号：US16840176
申请日：2020-04-03
Inventor： Zhidong YUAN , Taejin KIM , Yongqian LI , Lin SUN , Chao JIAO , Can YUAN , Zehua DING , Xuehuan FENG , Meng LI
IPC: G09G3/3233
Abstract: A pixel driving circuit, array substrate, display device and method for driving the pixel driving circuit are provided, the circuit includes: a control terminal and a first terminal of a driving switch circuit are respectively coupled to a first terminal of a data input switch circuit and an anode of a light-emitting device, and two terminals of a storage capacitor are respectively coupled to the control terminal of the driving switch circuit and the anode of the light-emitting device, two terminals of an intrinsic capacitor are respectively coupled to a cathode and the anode of the light-emitting device, a first terminal and a second terminal of a reset switch circuit are respectively coupled to the anode and the cathode of the light-emitting device, a capacitance of the intrinsic capacitor is greater than or equal to a preset multiple of a capacitance of the storage capacitor.
-
-
-
-
-
-
-
-
-
Search Results
499
records
(took 0.042 seconds)
