公开(公告)号：US06324097B1

公开(公告)日：2001-11-27

申请号：US09383373

申请日：1999-08-26

Applicant: Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

Inventor： Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

IPC: G11C1604

CPC classification number: H01L27/11521 ,  G11C2216/10 ,  H01L27/11558

Abstract: The present invention discloses a single poly non-volatile memory structure including a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and trapped in the floating gates, thereby preserving information in this memory structure.

Abstract translation: 本发明公开了一种单一的多元非易失性存储结构，其包括半导体衬底，两个有源区被隔离区划分。 掺杂有N型杂质的控制栅极嵌入在第一有源区中，并且在其上形成第一浮栅。 在第二有源区的衬底上形成第二浮栅，并且在衬底中的第二有源区的相对侧注入两个掺杂区。 采用浮动栅极线连接第一和第二浮栅，以确保两个浮动栅极处于相同的电位。 当控制栅极偏置到电压电平时，电压电平将耦合到第一浮置栅极，以便使第二浮置栅极与第一浮置栅极保持相同的电位。 虽然一个掺杂区域被偏置到电压电平，但电子将从另一个掺杂区域弹出并被捕获在浮动栅极中，从而保留该存储器结构中的信息。