Abstract:
An apparatus comprising a first amplifier, a second amplifier and a control circuit. The first amplifier may be configured to present a first amplified output signal in response to an input signal. The second amplifier may be configured to present a second amplified output signal to provide a shaped signal peaking response in response to the input signal. The first and second amplified output signals are generally combined. The control circuit may be configured to control a ratio between the first amplified output signal and the second amplified output signal. The ratio controls an amount of the peaking response.
Abstract:
An apparatus for sensing a vehicle crash condition includes an accelerometer (20) for sensing a vehicle crash condition and for providing a signal having a characteristic indicative of the vehicle crash condition. A crash velocity determining circuit (74) determines a crash velocity value (78) from the accelerometer. Crash metric determining circuits (80, 82, 94, 96, 104, 108) determine crash metric values functionally related to acceleration. Threshold determining circuits (88, 98, 112) determining associated threshold values functionally related to the determined crash velocity value (78). Comparators (90, 100, 116) compare the determined crash metric values against associated threshold values. A controller (34) provides a control signal to control actuation of a restraining device in response to the comparison. A shape monitoring circuit (120) determines if the shape of the acceleration signal matches a predetermined shape. If the shape matches, the controller provides the control signal.
Abstract:
A double balanced modulator-demodulator consisting of two pairs of field ect transistors. A field effect transistor is connected in series between the source electrodes of each of the field effect transistor pairs. The field effect transistors making up each pair are biased so that they operate in the saturated mode. Each of the transistors connected between the source electrodes of the transistor pairs are biased to operate in the linear mode such that drain current varies linearly with drain voltage. A first input signal is connected across the gate electrodes of the transistor pairs while a second input signal is connected across the gate electrodes of the connecting transistors. Bias for each of the transistor pairs is provided by means of a field effect transistor connected between the source electrodes of the transistor pairs and ground. The gates and source electrodes of transistors forming the bias circuit are connected to ground. The outputs of the two pairs are connected in parallel such that the differential output current is proportional to the product of the input signals.