公开(公告)号：US06707139B2

公开(公告)日：2004-03-16

申请号：US09928497

申请日：2001-08-14

Applicant: Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

Inventor： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC: H01L2348

CPC classification number: H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract translation: 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。