公开(公告)号：US20100182829A1

公开(公告)日：2010-07-22

申请号：US12691293

申请日：2010-01-21

Applicant: Kiyoshi Nakai

Inventor： Kiyoshi Nakai

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1096 ,  G11C7/24 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2213/79

Abstract: To provide a plurality of write amplifiers that perform a data write operation upon memory cells and a write control circuit that controls a timing of a data write operation performed by the write amplifiers. When a data write operation using another write amplifier is requested while a data write operation using a predetermined write amplifier is performed, the write control circuit suspends the data write operation using the predetermined write amplifier. The suspended data write operation is performed again simultaneously with the data write operation using the other write amplifier. Accordingly, random column access like that of a DRAM can be realized by simple control.

Abstract translation: 提供对存储单元执行数据写入操作的多个写入放大器和控制由写入放大器执行的数据写入操作的定时的写入控制电路。 当在执行使用预定写放大器的数据写入操作时请求使用另一个写放大器的数据写操作时，写控制电路使用预定的写放大器暂停数据写操作。 暂停数据写入操作再次与使用另一个写放大器的数据写操作同时执行。 因此，可以通过简单的控制来实现类似于DRAM的随机列访问。

公开(公告)号：US07760545B2

公开(公告)日：2010-07-20

申请号：US11955879

申请日：2007-12-13

Applicant: Kiyoshi Nakai

Inventor： Kiyoshi Nakai

IPC: G11C11/00

CPC classification number: G11C17/165 ,  G11C11/005 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: A semiconductor memory device is provided that has a storage unit that includes an interlayer insulation film, a lower electrode layer embedded in the interlayer insulation film, and a recording layer and an upper electrode layer provided on the interlayer insulation film. When a predetermined current is passed to the storage unit, the recording layer is heated by substantially exceeding a melting point, and a cavity is formed near the interface between the recording layer and the lower electrode layer. As a result, the recording layer is physically separated from the lower electrode layer, and no current flows through the storage unit. When the recording layer is physically separated from the lower electrode layer, these layers cannot be returned to the contact state again. Therefore, information can be stored irreversibly.

Abstract translation: 提供一种半导体存储器件，其具有存储单元，该存储单元包括层间绝缘膜，嵌入在层间绝缘膜中的下电极层，以及设置在层间绝缘膜上的记录层和上电极层。 当预定电流通过存储单元时，记录层被基本上超过熔点加热，并且在记录层和下电极层之间的界面附近形成空腔。 结果，记录层与下电极层物理分离，并且没有电流流过存储单元。 当记录层与下电极层物理分离时，这些层不能再次返回到接触状态。 因此，可以不可逆地存储信息。

公开(公告)号：US20100135063A1

公开(公告)日：2010-06-03

申请号：US12628835

申请日：2009-12-01

Applicant: Kiyoshi Nakai ,  Shuichi Tsukada

Inventor： Kiyoshi Nakai ,  Shuichi Tsukada

IPC: G11C7/12 ,  G11C11/00 ,  G11C7/00

CPC classification number: G11C7/18 ,  G11C2207/005

Abstract: A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group of bit lines and one of the second group of bit lines are selected in parallel. A reference potential is supplied to at least one of the first non-selected bit lines adjacent to the first selected bit line selected from the first group of bit lines, and to at least one of the second non-selected bit lines adjacent to the second selected bit line selected from the first group of bit lines. At least one of remaining ones of the first and second non-selected bit lines is set into a floating state.

Abstract translation: 半导体器件包括：第一读/写放大器; 第二读/写放大器; 属于第一读/写放大器的第一组位线; 属于第二读/写放大器的第二组位线，并与第一组位线混合。 第一组位线之一和第二组位线之一并行选择。 将参考电位提供给与从第一组位线选择的第一选定位线相邻的第一非选择位线中的至少一个以及与第二组相邻的第二非选择位线中的至少一个 从第一组位线选择的选定位线。 将第一和第二未选择位线中的剩余的位中的至少一个设置为浮置状态。

公开(公告)号：US07590012B2

公开(公告)日：2009-09-15

申请号：US11845605

申请日：2007-08-27

Applicant: Kiyoshi Nakai

Inventor： Kiyoshi Nakai

IPC: G11C7/00

CPC classification number: G11C11/16 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/18 ,  H01L27/228 ,  H01L27/24

Abstract: Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS transistor having first end connected to write amplifier, second end connected to the bit line, and a gate, and controlled such that, if the write amplifier outputs a voltage level on power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the power-supply voltage and exceeding the voltage level of the power supply is applied to the gate. A second NMOS transistor has first end to which the block-select activating signal is applied, a gate connected to the power supply, and second end connected to the gate of the first NMOS transistor.

Abstract translation: 具有存储单元行选择性地减小的布局区域的半导体存储装置。 每个包括可编程电阻元件的存储单元通过位线连接以形成存储单元行。 用于选择存储单元行的选择电路包括第一NMOS晶体管，其第一端连接到写入放大器，连接到位线的第二端和栅极，并被控制，使得如果写入放大器在电源上输出电压电平 在块选择激活信号被激活之后，与门电压相加的电压与电源电压相同极性的电压超过电源电压。 第二NMOS晶体管具有施加块选择激活信号的第一端，连接到电源的栅极，以及连接到第一NMOS晶体管的栅极的第二端。

公开(公告)号：US07502252B2

公开(公告)日：2009-03-10

申请号：US11666160

申请日：2005-10-25

Applicant: Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

Inventor： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C2213/78 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

Abstract translation: 为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型， 形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够 写和读数据。 通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

公开(公告)号：US07492033B2

公开(公告)日：2009-02-17

申请号：US11602947

申请日：2006-11-22

Applicant: Homare Sato ,  Kiyoshi Nakai

Inventor： Homare Sato ,  Kiyoshi Nakai

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

Abstract: A semiconductor memory device includes a plurality of active regions, and a gate electrode in a fish bone shape arranged on each active region. In each active region, a plurality of source regions and a plurality of drain regions are arranged in a matrix manner. The source regions are commonly connected to a source line, and the drain regions are each connected to a lower electrode of a different memory element. According to the present invention, it is possible to assign three cell transistors connected in parallel to one memory element, so that an effective gate width is further increased.

Abstract translation: 半导体存储器件包括多个有源区，以及布置在每个有源区上的鱼骨形状的栅电极。 在每个有源区域中，以矩阵方式布置多个源极区域和多个漏极区域。 源极区域通常连接到源极线，并且漏极区域各自连接到不同存储元件的下部电极。 根据本发明，可以分配与一个存储元件并联的三个单元晶体管，从而进一步增加有效栅极宽度。

公开(公告)号：US07397695B2

公开(公告)日：2008-07-08

申请号：US11409097

申请日：2006-04-24

Applicant: Kiyoshi Nakai ,  Kazuhiko Kajigaya

Inventor： Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC: G11C7/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0076 ,  G11C2213/79

Abstract: A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1 is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10 then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1 is again turned on to write reset in the cell MC0.

Abstract translation: 与DRAM兼容性高的相变存储器。 如果连接到字线WL 0 L的单元MC 0具有低电阻，则流过其的电流高于在虚设单元MR 0中流动的电流，因此位线SA_B处于比其低的电位 的位线SA_T。 该差异由读出放大器SA放大并读出。 在由读出放大器锁存单元数据之前，NMOS晶体管MN 1被截止以将存储单元部分与读出放大器部分断开。 然后，NMOS晶体管MN 10导通，使得所选择的字线上的数据都处于设置状态。 如果要进行写入，则在来自作为I / O线的信号线LIO和RIO的读出放大器SA中进行写入。 但是，在存储单元中不执行写入。 在进行预充电指令以预充电字线WL 0 L之前，NMOS晶体管MN 1再次导通以在单元MC 0中写入复位。

公开(公告)号：US20080149912A1

公开(公告)日：2008-06-26

申请号：US11955879

申请日：2007-12-13

Applicant: Kiyoshi NAKAI

Inventor： Kiyoshi NAKAI

IPC: H01L47/00 ,  G11C11/00

CPC classification number: G11C17/165 ,  G11C11/005 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: A semiconductor memory device according to the present invention has a storage unit that includes an interlayer insulation film, a lower electrode layer embedded in the interlayer insulation film, and a recording layer and an upper electrode layer provided on the interlayer insulation film. When a predetermined current is passed to the storage unit, the recording layer is heated by substantially exceeding a melting point, and a cavity is formed near the interface between the recording layer and the lower electrode layer. As a result, the recording layer is physically separated from the lower electrode layer, and no current flows through the storage unit. When the recording layer is physically separated from the lower electrode layer, these layers cannot be returned to the contact state again. Therefore, information can be stored irreversibly.

Abstract translation: 根据本发明的半导体存储器件具有包括层间绝缘膜，嵌入层间绝缘膜中的下电极层以及设置在层间绝缘膜上的记录层和上电极层的存储单元。 当预定电流通过存储单元时，记录层被基本上超过熔点加热，并且在记录层和下电极层之间的界面附近形成空腔。 结果，记录层与下电极层物理分离，并且没有电流流过存储单元。 当记录层与下电极层物理分离时，这些层不能再次返回到接触状态。 因此，可以不可逆地存储信息。

公开(公告)号：US20060211231A1

公开(公告)日：2006-09-21

申请号：US11374074

申请日：2006-03-14

Applicant: Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

Inventor： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC: H01L21/3205

CPC classification number: G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

公开(公告)号：US06791132B2

公开(公告)日：2004-09-14

申请号：US10041601

申请日：2002-01-10

Applicant: Kiyoshi Nakai ,  Hidetoshi Iwai

Inventor： Kiyoshi Nakai ,  Hidetoshi Iwai

IPC: H01L31119

CPC classification number: H01L27/10882 ,  G11C5/063 ,  G11C11/4097 ,  H01L27/10814 ,  H01L27/10841 ,  H01L27/10897 ,  Y10S257/905

Abstract: In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL2a) are formed on a first layer, and lines M2 (e.g., M2a) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL1c) are formed on the first layer, and lines M2 (e.g., M2c) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M2 on the second layer can have a smaller line interval.

Abstract translation: 在旨在具有更小的读出放大器形成区域以与小尺寸位线匹配的半导体存储器件中，第一位线BL（例如，BL2a）形成在第一层上，并且线M2（例如，M2a） 形成在第二层上并连接到位于第一存储单元区域和读出放大器区域之间的第一连接区域中的第一位线。 第二位线BL（例如，BL1c）形成在第一层上，并且线M2（例如，M2c）形成在第二层上并且连接到位于第二存储单元区域和第二存储器单元区域之间的第二连接区域中的第二位线 感测放大器区域。 结果，第二层上的线M2可以具有较小的行间隔。