Abstract:
A method for testing a liquid crystal display panel is provided. The gate drivers are integrated onto the panel. The method includes simultaneously inputting a clock signal, an inverted clock signal, and a pull down signal into clock signal, inverted clock signal, and pull down signal input ends of the gate drivers. Simultaneously input a start pulse into the start pulse input end of the gate drivers to simultaneously turn on the gate lines in the selected area and thus simultaneously turning on the pixels in the selected area. At the same time, input test signals to all the data lines. The method of testing liquid crystal display panels disclosed by the present invention may be performed separately by areas, in which the panel is divided into different sub areas and is tested one area at a time.
Abstract:
A testing system of a liquid crystal display panel including a substrate, a driving circuit, a first testing pad, and a second testing pad is provided. The substrate includes a pixel array whose one side has a pixel testing area. The driving circuit is formed on the substrate and connected to the other side of the pixel testing area for providing a signal to the pixel array. The first testing pad is connected to the driving circuit. The second testing pad is connected to the pixel testing area. The testing method of the liquid crystal display panel includes: respectively testing whether the liquid crystal display panel and the pixel testing area have a defect and accordingly generating a first testing pattern and a second testing pattern; combining the first testing pattern and the second testing pattern to determine whether the defect occurs at the driving circuit or the pixel array.
Abstract:
A flat display apparatus comprising a shift register array is provided. The shift register array comprises a plurality of shift registers. At least one of these shift registers comprises a shift register unit, a first TFT, and a second TFT. The shift register unit is configured to receive an activation signal and comprises a first output terminal and a second output terminal. The gate of the first TFT is coupled to the first output terminal. The second electrode of the first TFT receives a clock signal. The gate of the second TFT is coupled to the first electrode of the first TFT. The second electrode of the second TFT is coupled to the second electrode of the first TFT. The first electrode of the second TFT is coupled to the second output terminal.
Abstract:
A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.