公开(公告)号：US20140042508A1

公开(公告)日：2014-02-13

申请号：US13951328

申请日：2013-07-25

Applicant: KILHO LEE

Inventor： KILHO LEE

IPC: H01L27/22 ,  H01L29/78

CPC classification number: H01L27/228 ,  H01L27/11585 ,  H01L29/78

Abstract: A semiconductor memory device includes a cell gate dielectric layer and a cell gate electrode disposed in a gate recess region crossing a cell active portion of a substrate, first and second doped regions disposed in the cell active portion at both sides of the gate recess region, respectively, at least one interlayer insulating layer covering the substrate, a data storage element electrically connected to the second doped region through a contact plug penetrating the at least one interlayer insulating layer, a mold layer covering the data storage element, and a bit line disposed in a cell groove formed in the mold layer. The bit line is in direct contact with a top surface of the data storage element.

Abstract translation: 半导体存储器件包括：单元栅极电介质层和设置在与衬底的单元有源部分交叉的栅极凹部区域中的单元栅极电极，设置在栅极凹部区域两侧的单元有源部分中的第一和第二掺杂区域， 覆盖基板的至少一个层间绝缘层，通过穿透至少一个层间绝缘层的接触插塞电连接到第二掺杂区域的数据存储元件，覆盖数据存储元件的模具层和布置的位线 在模具层中形成的电池槽中。 位线与数据存储元件的顶表面直接接触。

公开(公告)号：US20130221417A1

公开(公告)日：2013-08-29

申请号：US13686212

申请日：2012-11-27

Applicant: Kilho LEE ,  Ki Joon KIM ,  Se-Woong PARK

Inventor： Kilho LEE ,  Ki Joon KIM ,  Se-Woong PARK

IPC: H01L29/82

CPC classification number: H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.