公开(公告)号：US20090184702A1

公开(公告)日：2009-07-23

申请号：US12334996

申请日：2008-12-15

Applicant: Fabrice Blisson ,  Jean-Luc Moro ,  Marc Sabut

Inventor： Fabrice Blisson ,  Jean-Luc Moro ,  Marc Sabut

IPC: G05F3/16 ,  G05F3/04

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current.

Abstract translation: 电压调节器包括放大器和调节回路。 调节器包括连接到提供输入电压的端子的第一PMOS晶体管，与第一PMOS晶体管串联连接的第二PMOS晶体管。 这两个晶体管之间的节点定义了输出端子。 固定值的第一极化电流的第一源连接到第一晶体管的栅极，固定值的第二极化电流的第二源将第二晶体管连接到地。 第三个NMOS晶体管连接在两个电流源之间。 提供电路以自动修改相对于负载电流的极化电流中的至少一个。

公开(公告)号：US20080144413A1

公开(公告)日：2008-06-19

申请号：US11951001

申请日：2007-12-05

Applicant: Sebastien Barasinski ,  Francois Jacquet ,  Marc Sabut

Inventor： Sebastien Barasinski ,  Francois Jacquet ,  Marc Sabut

IPC: G11C7/12

CPC classification number: G11C11/419

Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Abstract translation: SRAM类型的存储器件具有由以行和列组织的基本存储器单元构成的存储器计划。 列的每个单元连接在读取操作期间预充电的两个位线之间。 电路被提供用于产生位线的预充电电压，其小于设备的额定电源电压。

公开(公告)号：US06906588B2

公开(公告)日：2005-06-14

申请号：US10451086

申请日：2001-12-14

Applicant: Michel Mouret ,  Marc Sabut ,  François Van Zanten

Inventor： Michel Mouret ,  Marc Sabut ,  François Van Zanten

IPC: H03G7/08 ,  H03F3/45

CPC classification number: H03G7/08

Abstract: A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.

Abstract translation: 具有差分输入和差分输出的可变增益放大器，包括衰减器块，接收输入电压并在几个输出上提供电压，每个电压等于衰减的输入电压; 差分跨导元件，每个具有连接到衰减器块的相应输出的第一输入，以及产生第一和第二正电流以及第一和第二负电流; 电流源组件，其适于根据模拟控制信号控制每个差分跨导元件的跨导; 以及输出块，其将第一和第二输入电流转换成差分输出电压，并且根据输出电压提供具有反馈电压的每个差分跨导元件的第二输入。