公开(公告)号：US5533008A

公开(公告)日：1996-07-02

申请号：US381602

申请日：1995-01-26

Applicant: Gary W. Grube ,  Timothy W. Markison ,  Matthew A. Pendleton ,  Mathew A. Rybicki

Inventor： Gary W. Grube ,  Timothy W. Markison ,  Matthew A. Pendleton ,  Mathew A. Rybicki

IPC: H04L27/26 ,  H04W24/06 ,  H04W92/02 ,  H04W92/12 ,  H04N7/14

CPC classification number: H04W92/02 ,  H04L27/2608 ,  H04W24/06 ,  H04W92/12

Abstract: In a communication system utilizing DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), infrastructure control channels are established in the following manner. Having obtained a plurality of site bit loading tables, the primary site (102) generates a control channel bit loading table from the plurality of site bit loading tables. From the control channel bit loading table, the primary site selects at least one carrier channel to function as the control channel. The selection is based on bandwidth requirements for the control channel.

Abstract translation: 在利用DMT技术将主站点（102）耦合到多个次要站点（104-108）的通信系统中，以下列方式建立基础设施控制信道。 在获得多个站点位加载表之后，主站点（102）从多个站点位加载表生成控制通道位加载表。 从控制通道位加载表中，主站点选择至少一个载波信道用作控制信道。 该选择基于控制信道的带宽要求。

公开(公告)号：US5373255A

公开(公告)日：1994-12-13

申请号：US98974

申请日：1993-07-28

Applicant: Jeffrey P. Bray ,  Matthew A. Pendleton ,  Steven E. Cozart

Inventor： Jeffrey P. Bray ,  Matthew A. Pendleton ,  Steven E. Cozart

IPC: H03L7/091 ,  H03D13/00 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03D13/004 ,  H03L7/089 ,  H03L7/093

Abstract: A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Abstract translation: 锁相环（PLL）（40）同时在时钟输出信号上具有相对低的功耗和相对低的抖动。 PLL（40）包括相位检测器（41）和与相位检测器（41）的输出端连接的相位误差累加器（42）。 相位误差累加器（42）以相对高的时钟速率对相位检测器（41）的输出进行采样，但是累积这些采样并以相对低的时钟速率将其输出提供给环路滤波器（43）。 因此，PLL（40）捕获短周期的相位延迟以维持低时钟输出信号抖动，而同时，环路滤波器（43）仅需要以相对较低的速率周期性地调整其输出，从而节省 功率。 相位检测器（41）检测相位检测器锁存器（60）上的亚稳态，并且解析为上升脉冲或下降脉冲，以进一步降低时钟输出信号抖动。