公开(公告)号：US20090237580A1

公开(公告)日：2009-09-24

申请号：US12052197

申请日：2008-03-20

Applicant: Ramesh KAKKAD ,  Hsiao-Wei KAO ,  Chung-Sheng LIN ,  Chih-Chung LIU

Inventor： Ramesh KAKKAD ,  Hsiao-Wei KAO ,  Chung-Sheng LIN ,  Chih-Chung LIU

IPC: G02F1/136 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/4908 ,  H01L27/1255

Abstract: A system for display images comprising a thin film transistor array substrate is disclosed. The system for display images comprises a substrate having a pixel area, a source/drain region overlying the substrate within an active layer in the pixel area, a bottom electrode overlying the substrate in the pixel area, a top electrode overlying the bottom electrode, a first dielectric layer disposed on the active layer, a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the bottom electrode and the top electrode and a gate disposed overlying the active layer, wherein the first and second dielectric layers are interposed between the gate and the active layer.

Abstract translation: 公开了一种包括薄膜晶体管阵列基板的显示图像系统。 用于显示图像的系统包括具有像素区域的衬底，覆盖像素区域中的有源层中的衬底的源极/漏极区域，覆盖在像素区域中的衬底的底部电极，覆盖底部电极的顶部电极， 设置在有源层上的第一电介质层，设置在第一电介质层上的第二电介质层，其中第二电介质层设置在底电极和顶电极之间，栅极设置在有源层上，其中第一和第二电介质层 层插入在栅极和有源层之间。

公开(公告)号：US6013565A

公开(公告)日：2000-01-11

申请号：US290227

申请日：1994-08-15

Applicant: Stephen J. Fonash ,  Ramesh Kakkad

Inventor： Stephen J. Fonash ,  Ramesh Kakkad

IPC: H01L21/20 ,  H01L31/0368 ,  H01L31/18 ,  H01L21/02

CPC classification number: H01L21/2022 ,  H01L31/03682 ,  H01L31/1864 ,  Y02E10/546 ,  Y02P70/521

Abstract: An ultra-thin highly electrically conductive material is prepared by depositing an amorphous material, substantially free of crystal growth-inducing nuclei and sites, onto a substrate. Deposition is preferably with a plasma deposition reactor, with semiconductor dopants introduced during deposition. Deposition time is preferably adjusted to create an amorphous film of a desired thickness, e.g., 200 .ANG.. After deposition, the amorphous film is annealed preferably with a rapid thermal annealing process for four minutes at 700.degree. C. The annealing triggers the creation of nuclei and subsequent large grain growth in the film, releases energy contained within the amorphous material, and helps drive crystallization and dopant activation. After annealing the material is completely crystallized, and contains large grains whose lateral dimensions can exceed the film thickness by a factor of fifty. Because the grain structure is large there are few grain boundaries to absorb dopants and carriers, and thus degrade electrical conductivity. Thin film material produced according to the present invention can exhibit conductivity 10.sup.10 times better than prior art materials at 200 .ANG. thickness. Such material is highly suitable in thin film semiconductor structures including buried gate memory devices, shallow emitter devices, as well as photovoltaic cells, X-ray and other radiation detectors. The disclosed annealing process will substantially improve conductivity of amorphous thin film materials, even if such materials are produced by methods other than deposition.

Abstract translation: 通过将基本上不含结晶生长诱导核和位点的无定形材料沉积到基底上来制备超薄高导电性材料。 沉积优选用等离子体沉积反应器，在沉积期间引入半导体掺杂剂。 优选调节沉积时间以产生所需厚度的无定形膜，例如200安培。 沉积后，非晶膜优选在700℃下快速热退火4分钟进行退火。退火触发了膜的产生和随后的大晶粒生长，释放出无定形材料内的能量，并且有助于驱动 结晶和掺杂剂活化。 退火之后，材料完全结晶，并且包含大的晶粒，其横向尺寸可以超过膜厚度五十倍。 由于晶粒结构大，因此难以吸收掺杂剂和载流子的晶界，导致导电性降低。 根据本发明生产的薄膜材料的电导率可以比现有技术的材料在200厚度下显示出1010倍。 这种材料非常适用于包括掩埋栅极存储器件，浅发射器件以及光伏电池，X射线和其它辐射探测器的薄膜半导体结构。 所公开的退火工艺将显着改善非晶薄膜材料的导电性，即使这些材料是通过沉积以外的方法生产的。