公开(公告)号：US20080197830A1

公开(公告)日：2008-08-21

申请号：US11951565

申请日：2007-12-06

Applicant: GUSTAVO JAMES MEHAS ,  SANDEEP AGARWAL ,  JAYANT VIVREKAR ,  XIAOLE CHEN

Inventor： GUSTAVO JAMES MEHAS ,  SANDEEP AGARWAL ,  JAYANT VIVREKAR ,  XIAOLE CHEN

IPC: H03L7/085 ,  G05B24/02

CPC classification number: H03L7/0992 ,  H03L7/085 ,  H03L7/093

Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Abstract translation: 电路包括用于产生同步信号的数字锁相环和用于响应于来自数字锁相环的同步信号来提供调节的输出电压的电压调节器。