公开(公告)号：US09621143B2

公开(公告)日：2017-04-11

申请号：US14076020

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Osborn ,  Michael J. Tresidder ,  Aaron J. Grenat ,  Joseph Kidd ,  Priyank Parakh ,  Steven J. Kommrusch

IPC: G06F9/455 ,  G06F17/50 ,  H03K5/153

CPC classification number: H03K5/153 ,  G06F17/5009 ,  G06F17/5031 ,  G06F2217/84

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.