公开(公告)号：US20190026243A1

公开(公告)日：2019-01-24

申请号：US15653456

申请日：2017-07-18

Applicant: ARM Limited

Inventor： Damian Piotr Modrzyk ,  David Brown ,  Ozgur Ozkurt

IPC: G06F13/40 ,  G06F5/06 ,  G06F3/00

CPC classification number: G06F5/065 ,  G06F13/385 ,  G06F2205/067 ,  G06T1/60 ,  G09G5/00

Abstract: A display controller for a data processing system comprises two sets of display processing units, each set of display processing units comprising an input unit operable to read at least one input surface, a processing unit operable to process one or more input surfaces to generate an output surface, and an output unit operable to provide an output surface for display to a display. The display controller also includes internal data path via which pixel data of a surface may be passed between the sets of display processing units, and a control unit that can selectively activate one or both of the sets of display processing units to process one or more input surfaces to generate one or more output surfaces for display.

公开(公告)号：US20170140500A1

公开(公告)日：2017-05-18

申请号：US15347058

申请日：2016-11-09

Applicant: ARM Limited

Inventor： Daren Croxford ,  Damian Piotr Modrzyk ,  Piotr Tadeusz Chrobak

IPC: G06T1/60 ,  G09G5/393 ,  G09G5/395 ,  G06T1/20

Abstract: A display controller 10 comprises a first display processing core 20 comprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display 3, and a first write-out stage 27 operable to write data of an output surface to external memory 1, and a second display processing core 40 comprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display 5. The display controller 10 also comprises an internal data path 30 for passing data of an output surface from the first display core 20 to the second display core 40.