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公开(公告)号：US20180146158A1
公开(公告)日：2018-05-24
申请号：US15810090
申请日：2017-11-12
Applicant: Arm Limited
Inventor： Michal Karol Bogusz , Piotr Tadeusz Chrobak
CPC classification number: H04N7/012 , G06T3/40 , G09G5/363 , G09G5/391 , G09G2310/0229 , G09G2340/0407 , G09G2340/0492 , G09G2340/125 , H04N5/2628
Abstract: A data processing system includes a scaler 18 operable to scale a received input data array to provide a scaled output version of the input data array. When it is desired to produce a de-interlaced and scaled output version of an input data array 21, 22, the input data array 21, 22 is provided to the scaler 18, and the scaler 18 scales the input data array 21, 22 so as to simultaneously de-interlace and scale the input data array and to produce a de-interlaced and scaled output version of the input data array.
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公开(公告)号：US20170140500A1
公开(公告)日：2017-05-18
申请号：US15347058
申请日：2016-11-09
Applicant: ARM Limited
Inventor： Daren Croxford , Damian Piotr Modrzyk , Piotr Tadeusz Chrobak
Abstract: A display controller 10 comprises a first display processing core 20 comprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display 3, and a first write-out stage 27 operable to write data of an output surface to external memory 1, and a second display processing core 40 comprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display 5. The display controller 10 also comprises an internal data path 30 for passing data of an output surface from the first display core 20 to the second display core 40.
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公开(公告)号：US10659723B2
公开(公告)日：2020-05-19
申请号：US15810090
申请日：2017-11-12
Applicant: Arm Limited
Inventor： Michal Karol Bogusz , Piotr Tadeusz Chrobak
Abstract: A data processing system includes a scaler 18 operable to scale a received input data array to provide a scaled output version of the input data array. When it is desired to produce a de-interlaced and scaled output version of an input data array 21, 22, the input data array 21, 22 is provided to the scaler 18, and the scaler 18 scales the input data array 21, 22 so as to simultaneously de-interlace and scale the input data array and to produce a de-interlaced and scaled output version of the input data array.
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公开(公告)号：US20180101928A1
公开(公告)日：2018-04-12
申请号：US15287492
申请日：2016-10-06
Applicant: ARM Limited
Inventor： Michal Karol Bogusz , Piotr Tadeusz Chrobak
CPC classification number: G09G5/397 , G09G5/14 , G09G5/377 , G09G2340/02 , G09G2370/10 , G09G2370/12 , G09G2370/16 , H04N5/28
Abstract: In a display controller of a data processing system, when composing two or more input surfaces to generate a composited surface comprising the two or more input surfaces, data indicating a border between different input surfaces in the composited surface is associated with the composited surface. The data indicative of the border between two input surfaces in the composited surface is then used to control subsequent processing, such as compression and/or filtering, of the composited surface.
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公开(公告)号：US10592146B2
公开(公告)日：2020-03-17
申请号：US15635099
申请日：2017-06-27
Applicant: ARM Limited
Inventor： Sharjeel Saeed , Kushan Vijaykumar Vyas , Michal Karol Bogusz , Piotr Tadeusz Chrobak , Ozgur Ozkurt
Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.
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Patent Agency Ranking
公开(公告)号：US10565966B2
公开(公告)日：2020-02-18
申请号：US15287492
申请日：2016-10-06
Applicant: ARM Limited
Inventor： Michal Karol Bogusz , Piotr Tadeusz Chrobak
Abstract: In a display controller of a data processing system, when composing two or more input surfaces to generate a composited surface comprising the two or more input surfaces, data indicating a border between different input surfaces in the composited surface is associated with the composited surface. The data indicative of the border between two input surfaces in the composited surface is then used to control subsequent processing, such as compression and/or filtering, of the composited surface.
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公开(公告)号：US10510323B2
公开(公告)日：2019-12-17
申请号：US15347058
申请日：2016-11-09
Applicant: ARM Limited
Inventor： Daren Croxford , Damian Piotr Modrzyk , Piotr Tadeusz Chrobak
Abstract: A display controller 10 comprises a first display processing core 20 comprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display 3, and a first write-out stage 27 operable to write data of an output surface to external memory 1, and a second display processing core 40 comprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display 5. The display controller 10 also comprises an internal data path 30 for passing data of an output surface from the first display core 20 to the second display core 40.
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公开(公告)号：US20200066233A1
公开(公告)日：2020-02-27
申请号：US16667658
申请日：2019-10-29
Applicant: Arm Limited
Inventor： Daren Croxford , Damian Piotr Modrzyk , Piotr Tadeusz Chrobak
Abstract: A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.
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公开(公告)号：US10276125B2
公开(公告)日：2019-04-30
申请号：US15281451
申请日：2016-09-30
Applicant: ARM Limited
Inventor： Piotr Tadeusz Chrobak , Michal Karol Bogusz
Abstract: In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.
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公开(公告)号：US20180095677A1
公开(公告)日：2018-04-05
申请号：US15281451
申请日：2016-09-30
Applicant: ARM Limited
Inventor： Piotr Tadeusz Chrobak , Michal Karol Bogusz
CPC classification number: G09G5/001 , G06F3/14 , G06F5/06 , G06F5/14 , G09G5/14 , G09G5/393 , G09G5/397 , G09G2340/12
Abstract: In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.
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