公开(公告)号：US20140365751A1

公开(公告)日：2014-12-11

申请号：US14273723

申请日：2014-05-09

Applicant: ARM LIMITED

Inventor： Ian Michael CAULFIELD ,  Max BATLEY ,  Peter Richard GREENHALGH

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3017 ,  G06F9/3557

Abstract: A data processing apparatus has at least one processing pipeline having first, second and third pipeline stages. The first pipeline stage detects whether a stream of instructions to be processed includes a predetermined instruction sequence comprising first and second instructions for performing first and second operand generation operations, where the second operand generation operation is dependent on an outcome of the first. In response to detecting this instruction sequence, the first pipeline stage generates a modified stream of instructions in which at least the second instruction is replaced with a third instruction for performing a combined operand generation operation having the same effect as the first and second operand generation operations. As the third instruction can be scheduled independently of the first instruction, processing performance of the pipeline can be improved.

Abstract translation: 数据处理装置具有至少一个具有第一，第二和第三流水线级的处理流水线。 第一流水线级检测待处理的指令流是否包括预定指令序列，该预定指令序列包括用于执行第一和第二操作数产生操作的第一和第二指令，其中第二操作数产生操作取决于第一操作数的结果。 响应于检测到该指令序列，第一流水线级产生修改的指令流，其中至少第二指令被替换为用于执行具有与第一和第二操作数产生操作相同效果的组合操作数生成操作的第三指令 。 由于可以独立于第一指令来调度第三指令，所以可以提高流水线的处理性能。