公开(公告)号：US20180260218A1

公开(公告)日：2018-09-13

申请号：US15452150

申请日：2017-03-07

Applicant: Vinodh Gopal

Inventor： Vinodh Gopal

IPC: G06F9/26 ,  G06F9/30 ,  G06F9/345

CPC classification number: G06F9/44547 ,  G06F1/3203 ,  G06F1/3287 ,  G06F8/447 ,  G06F8/47 ,  G06F9/268 ,  G06F9/30061 ,  G06F9/345 ,  G06F9/3557 ,  G06F9/3877 ,  G06F9/44521 ,  G06F9/5066 ,  G06F15/76

Abstract: Instruction set architectures (ISA) for fine-grained heterogeneous processing and associated processors, methods, and compilers. The ISA includes instructions that are configured to be executed on processors having heterogeneous cores implementing different micro-architectures. Mechanisms are provided to enable respective code segments to be compiled/assembled for a target processor (or processor family) with heterogeneous cores and have appropriate code segments that has been compiled for specific types of processor core micro-architectures be dynamically called at run-time via execution of the ISA instructions. The ISA instructions include both unconditional and conditional branch and call instructions, in addition to instructions that support processors with three or more different types of cores. The instructions are configured to support dynamic migration of instruction threads across heterogeneous cores while adding substantially no overhead. A compiler is also provided to generate and assemble opcode segments configured to be executed on processors with heterogeneous cores.

公开(公告)号：US20170083343A1

公开(公告)日：2017-03-23

申请号：US14942461

申请日：2015-11-16

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger

IPC: G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The disclosed technology can be used for executing and committing instruction blocks of a block-based processor architecture out-of-order. In one example of the disclosed technology, an apparatus can include a plurality of block-based processor cores which can include a first group of cores and a second group of cores. The first group of cores can be configured to commit instruction blocks of the set of instruction blocks in a sequential program order. The second group of cores can be configured to commit instruction blocks of the set of instruction blocks out-of-order relative to the sequential program order.

公开(公告)号：US20170083326A1

公开(公告)日：2017-03-23

申请号：US15012662

申请日：2016-02-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/30 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.

公开(公告)号：US09495163B2

公开(公告)日：2016-11-15

申请号：US14573193

申请日：2014-12-17

Applicant: ARM Limited

Inventor： Nigel John Stephens ,  David James Seal

IPC: G06F9/355 ,  G06F9/345 ,  G06F9/30 ,  G06F9/34 ,  G06F12/10

CPC classification number: G06F9/3557 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/345 ,  G06F2212/657

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

公开(公告)号：US09329850B2

公开(公告)日：2016-05-03

申请号：US14313358

申请日：2014-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind ,  Valentina Salapura

IPC: G06F9/45 ,  G06F9/445 ,  G06F9/30

CPC classification number: G06F8/52 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3557 ,  G06F9/44557

Abstract: Relocation of instructions that use relative addressing. Metadata relating to an instruction that uses relative addressing to access data and is to be relocated is stored prior to relocation. Based on relocating the instruction from one memory location to another memory location, a determination is made of an address to be used to access the data by the instruction. The determining is based on at least one of the metadata or an address of the another memory location. The instruction is executed at the another memory location, and the determined address is used to access the data.

Abstract translation: 重新定位使用相对寻址的指令。 在重定位之前存储与使用相对寻址访问数据并将被重新定位的指令相关的元数据。 基于将指令从一个存储器位置重新定位到另一个存储器位置，确定用于通过指令访问数据的地址。 该确定基于另一个存储器位置的元数据或地址中的至少一个。 该指令在另一个存储器位置执行，并且确定的地址用于访问数据。

公开(公告)号：US20150347146A1

公开(公告)日：2015-12-03

申请号：US14291693

申请日：2014-05-30

Applicant: International Business Machines Corporation

Inventor： Michael K. Gschwind

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/324 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/4486

Abstract: Embodiments relate to a system for relative offset branching in a reduced instruction set computing (RISC) architecture. One aspect is a system that includes memory and a processing circuit communicatively coupled to the memory. The system is configured to perform a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A relative offset value is acquired from the instruction stream. The relative offset value is formatted as an offset relative to a program counter value and sized as a multiple of the fixed instruction width. The relative offset value is added with the program counter value to form a branch target address value. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.

Abstract translation: 实施例涉及在精简指令集计算（RISC）架构中相对偏移分支的系统。 一个方面是包括存储器和通信地耦合到存储器的处理电路的系统。 该系统被配置为执行包括从具有固定指令宽度的指令流获取分支指令的方法。 从指令流获取相对偏移值。 相对偏移值被格式化为相对于程序计数器值的偏移量，并且被设置为固定指令宽度的倍数。 相对偏移值加上程序计数器值，形成分支目标地址值。 分支目标地址值根据分支指令加载到程序计数器中。 基于程序计数器中的分支目标地址值，将指令流的执行重定向到下一条指令。

公开(公告)号：US20090182988A1

公开(公告)日：2009-07-16

申请号：US11972780

申请日：2008-01-11

Applicant: Dan F. Greiner ,  Timothy J. Slegel

Inventor： Dan F. Greiner ,  Timothy J. Slegel

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/30167 ,  G06F9/3557

Abstract: A method, system and program product for comparing two operands wherein one operand is obtained from memory wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter.

Abstract translation: 一种用于比较两个操作数的方法，系统和程序产品，其中一个操作数从存储器获得，其中存储器操作数的地址基于程序计数器的偏移而不是明确定义的地址位置。 偏移量由符号扩展的指令的立即字段定义，并在被添加到程序计数器的值时作为半字地址对齐。

公开(公告)号：US06343357B1

公开(公告)日：2002-01-29

申请号：US09632332

申请日：2000-08-03

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F1500

CPC classification number: G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract translation: 采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点 通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。 并且，通过注意代码位来执行编码除法的控制。

公开(公告)号：US5991545A

公开(公告)日：1999-11-23

申请号：US478730

申请日：1995-06-07

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F9/28 ,  G06F7/483 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/537 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/22

CPC classification number: G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract translation: 这里公开了采用通用寄存器方法的微计算机MCU。 微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过 采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US5226131A

公开(公告)日：1993-07-06

申请号：US751002

申请日：1991-08-28

Applicant: Victor G. Grafe ,  James E. Hoch

Inventor： Victor G. Grafe ,  James E. Hoch

IPC: G06F9/32 ,  G06F9/44

CPC classification number: G06F9/3557 ,  G06F9/32 ,  G06F9/4436

Abstract: A sequencing and data fanout mechanism is provided for a dataflow processor is activated by an input token which causes a sequence of operations to occur by initiating a first instruction to act on data contained within the token and then executing a sequential thread of instructions identified by either a repeat count and an offset within the token, or by an offset within each preceding instruction.

Abstract translation: 提供了排序和数据扇出机制，用于由输入令牌激活的数据流处理器，该输入令牌通过发起对包含在令牌内的数据作用的第一指令，然后执行由以下任一 令牌内的重复计数和偏移量，或每个前一条指令中的偏移量。