Hybrid bacon-shor surface codes in a concatenated cat-qubit architecture

    公开(公告)号:US11983601B2

    公开(公告)日:2024-05-14

    申请号:US17218046

    申请日:2021-03-30

    CPC classification number: G06N10/00 G01R33/0354 G06F11/1012 H10N60/12

    Abstract: A hybrid Bacon-Shor surface code is implemented using a fault tolerant quantum computer comprising hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit. The hybrid Bacon-Shor surface code only couples four phononic modes per given ATS, reducing cross-talk as compared to other systems that couple more phononic modes per ATS. Also, measurements are performed such that three parity measurements are taken between a phononic readout mode and a transmon qubit in a given syndrome measurement cycle.

    Error correction decoding techniques for lattice surgery

    公开(公告)号:US11900221B1

    公开(公告)日:2024-02-13

    申请号:US17545895

    申请日:2021-12-08

    CPC classification number: G06N10/70 G06N10/20

    Abstract: A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.

    TOFFOLI GATE DISTILLATION FROM TOFFOLI MAGIC STATES

    公开(公告)号:US20220156441A1

    公开(公告)日:2022-05-19

    申请号:US17098240

    申请日:2020-11-13

    Abstract: A top-down distillation process for preparing low-error rate Toffoli gates utilizes Toffoli magic states as inputs to the distillation process. Multiple Toffoli magic states are used to distill a low-error rate Toffoli gate via one round of distillation. Lattice surgery operations are performed to distill the low-error rate Toffoli gate from the multiple Toffoli magic states. Each round of lattice surgery operations acts on a check qubit associated with the low error rate Toffoli gate being distilled. Errors introduced during the distillation (if non-trivial) will be manifest in the check qubit. Thus, the check qubit is measured subsequent to performing the lattice surgery operations to verify that the distilled Toffoli gate is very likely to be provide a correct result.

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